Lead architecture and RTL implementation for 100G/400G/800G Ethernet ASIC subsystems. Define microarchitecture, implement IEEE 802.3 MAC/PCS/PMA features including FEC and lane alignment, integrate SerDes IP, and drive timing, clock-domain, power, lint, CDC/RDC, synthesis, formal verification, tape-out, and bring-up activities. Mentor designers and collaborate with physical design teams on advanced-node ASIC development.
Principal RTL Lead – High Speed Ethernet (ASIC)
Company Overview:
MosChip is a semiconductor and embedded system design company with a focus on Embedded, Turnkey ASICs, Mixed Signal IP, Semiconductor & Product Engineering and IoT solutions catering to Aerospace & Defense, Consumer Electronics, Automotive, Medical and Networking & Telecommunications.
We are seeking a seasoned Principal RTL Lead to spearhead the development of next-generation Ethernet subsystems. This isn't just about moving packets; it's about defining the architecture for 400G, 800G, and beyond. As the technical lead, you will own the logic that powers the world's fastest data centers, ensuring ultra-low latency and rock-solid reliability at massive scale.
Candidate will lead a high-caliber team of designers to implement high-speed Ethernet IP (MAC/PCS/PMA) into our custom ASIC silicon. Your role is a blend of deep technical execution and strategic mentorship—steering the team through the complexities of multi-lane alignment, Forward Error Correction (FEC), and high-speed clocking challenges.
Key Responsibilities
- Technical Leadership: Act as the primary architect for the Ethernet subsystem. You'll define micro-architecture for high-bandwidth data paths and complex control logic.
- Protocol Mastery: Own the implementation of IEEE 802.3 standards, including RS-FEC (254, 256) , multi-lane distribution (MLD), and auto-negotiation/link training (AN/LT).
- High-Speed Logic Design: Solve the "hard problems" ofnetworking: managing massive bus widths (eg, 1024-bit+), minimizing logic depth fortiming closure, and handling complex CDC across asynchronous boundaries.
- Front-End Integration: Lead the integration of third-party SerDes IP and ensure seamless interoperability between the electrical physical layer and the digital MAC.
- Design for Excellence: Drive best practices in coding (SystemVerilog), power optimization (UPF), and lint/CDC/RDC analysis to ensure first-pass silicon success.
- The Track Record: 10+ years of experience in RTL design with at least 3-4 successful tape-outs in advanced process nodes (7nm, 5nm, or 3nm).
- Ethernet Expertise: Deep, hands-on experience with 100G/400G/800G Ethernet protocols and the underlying sub-layers (MAC, PCS, FEC).
- ASIC Lifecycle: Expert knowledge of the full front-end ASIC flow—from architectural spec to synthesis, formal verification, and post-silicon bring-up.
- High-Speed Design: Proven ability to close timing on high-frequency designs () and manage complex clocking architectures.
- Scripting Power: Proficiency in Python or Perl for creating sophisticated design-generation and analysis tools.
- Desirable skills:
- Experience with IEEE 1588 (PTP) hardware stamping for precision timing.
- Familiarity with CXL or PCIe Gen 5/6 protocols.
- Direct experience working with physical design teams on timing and congestion mitigation.
Experience: 10+ Years
Location: Bay Area, California
Contract Duration: 6 Plus months
Shift: General
Work Week: Monday to Friday
Quick Links:
Who we are? : https://www.youtube.com/watch?v=4nvbzE-eUGk
How we train? : https://www.youtube.com/watch?v=Yy5GtKP7ozk
Contact: : www.moschip.com
MosChip Santa Clara, California, USA Office
4699 Old Ironsides Dr Ste 270, Santa Clara, United States, 95054
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