Array Labs Logo

Array Labs

Printed Circuit Board Design Engineer

Posted 3 Days Ago
Be an Early Applicant
In-Office
Redwood City, CA, USA
150K-250K Annually
Mid level
In-Office
Redwood City, CA, USA
150K-250K Annually
Mid level
Design, lay out, validate, manufacture, and test spacecraft printed circuit assemblies for radar payloads and onboard processing systems. Responsibilities include architecture, requirements, component selection, schematic capture, system trades, prototyping, hardware bring-up, debugging, qualification, and manufacturing management. The engineer collaborates with RF, digital, software, firmware, mechanical, antenna, and systems teams while improving designs based on laboratory, environmental, and on-orbit testing.
The summary above was generated by AI

About Us

Array Labs builds advanced radar systems to help humanity understand and respond to changes across the physical world. 

We’re launching a coordinated fleet of radar satellites to create a high-resolution 3D map of the Earth – updated in real time – enabling faster, smarter decision-making for government and commercial organizations supporting disaster response, infrastructure resilience, and mission-critical geopolitical intelligence.

We design and build our satellites end-to-end, producing the world’s most advanced earth observation satellites. Our fleet will deliver unprecedented levels of accuracy, coverage, and responsiveness to power critical insights precisely where they’re needed most.

About the Job
As a Board Design Engineer, you will design, lay out, and validate the printed circuit assemblies that power Array’s radar payloads and on-orbit processing systems. Your work will span high-density digital and mixed-signal designs, power regulation modules, RF-interfaces, and compute hardware operating under the constraints of small satellite platforms. You will take boards from schematic through layout, manufacturing, bring-up, and qualification, working closely with RF, antenna, digital, mechanical, and systems engineers. The boards you develop will directly influence Array’s signal integrity, processing throughput, thermal behavior, and overall radar system capability.

As part of our quickly growing engineering team, you will play a critical role in the design of the world’s most advanced radar satellite constellation—one that will significantly improve humanity’s ability to rapidly and comprehensively understand our changing planet.


Responsibilities

  • Develop advanced electronic platforms, from architecture to manufacturing
  • Work closely with software, firmware, RF, antenna, digital, and mechanical design engineers to design and validate state-of-the-art spacecraft electronics
  • Create requirements, perform system trades, select components, capture schematics, design complex electronic assemblies and manage manufacturing
  • Lead prototyping, hardware bring-up, debug, manufacturing, and test campaigns.
  • Rapidly iterate on and improve electronic designs based on laboratory, environmental and on-orbit testing
 
Basic Qualifications
  • Experience in board design and layout
  • Experience in electronics manufacture, bring-up, and test 
  • Excellent teamwork and communication skills
  • Learns new concepts rapidly, completely, and in a self-directed manner
  • High levels of self-motivation and personal accountability
  • Ability to work in a fast-paced environment under significant time constraints
 
Preferred Skills & Experience
  • Bachelor in electrical engineering, or a related field
  • 4+ years of electrical engineering work experience with full-life cycle development (concept to production) of consumer electronics, power electronics, communications, automotive, aerospace, and/or robotics
  • Background in high-speed board design, simulation, and validation techniques including PCB stack-up, PCB fabrication, floorplanning, component selection, placement and routing, simulation and measurement
  • Hands-on experience laying out high-performance platforms including compute (SoCs, FPGAs, MCUs), storage (DDR, SSDs), high-speed interfaces (PCIe, SPI, JESD204B), RF components (PAs, LNAs, switches)
  • Expertise in signal and power integrity simulation and measurement
  • Hands-on experience with test equipment such as oscilloscopes and network analyzers
 

Compensation & Benefits

Our hiring and compensation strategy is simple: find uncommonly good people and pay them uncommonly well.

We offer high flexibility between salary and equity-based compensation. Final candidates can choose from three compensation mixes: low, medium, or high equity. Equity is a significant component of total compensation, and we aim to provide meaningful ownership for this role.

Full-time employees enjoy a comprehensive benefits package including health, dental, and vision coverage, 401(k) plan with company match, commuter benefits, and more.


Interview Process

We will conduct interviews via Google Meet with the potential for an onsite visit; the typical process takes around 3–5 weeks to complete from start to finish.


Why Join Array

At Array Labs, deep technical expertise meets relentless impact. We prioritize curiosity over hierarchy and bold engineering over incremental gains. Our world-class team across hardware engineering, software, and aerospace works collaboratively to push boundaries and move fast.

Our values:

●  Build What Matters: Create technology that serves customers and advances humanity
●  Innovate Together: Stay curious, collaborate openly, push boundaries as one team
●  Employee Centric: Put our people first with a culture of trust, respect, and opportunity
 

Join industry-leading experts to deliver unprecedented insights about our planet and build the future of Earth observation.


ITAR Requirements

To conform to U.S. Government space technology export regulations, including the International Traffic in Arms Regulations (ITAR) you must be a U.S. citizen, lawful permanent resident of the U.S., protected individual as defined by 8 U.S.C. 1324b(a)(3), or eligible to obtain the required authorizations from the U.S. Department of State.


Equal Opportunity Employer

Array Labs is an Equal Opportunity Employer. Employment decisions are made on the basis of merit, competence, and job qualifications and will not be influenced in any manner by gender, color, race, ethnicity, national origin, sexual orientation, religion, age, gender identity, veteran status, disability status, marital status, mental or physical disability or any other legally protected status.

If you require a reasonable accommodation during the application or interview process, please let us know.

 
HQ

Array Labs Palo Alto, California, USA Office

Palo Alto, CA, United States

Similar Jobs

53 Minutes Ago
Hybrid
15-20 Hourly
Junior
15-20 Hourly
Junior
eCommerce • Fashion • Retail • Sales • Wearables • Design
Provides customer service and sales support in a luxury retail store. Responsibilities include welcoming clients, operating POS and cash wrap, suggesting products, processing shipments and transfers, maintaining stock levels, replenishing the sales floor, executing visual merchandising updates, supporting social media engagement, and following housekeeping and loss-prevention procedures. Requires flexible availability, physical ability to handle stockroom and sales-floor tasks, and strong communication and organizational skills.
Top Skills: InternetIpadLaptopMobile PosPosWalkie-Talkie
54 Minutes Ago
In-Office
99K-162K Annually
Senior level
99K-162K Annually
Senior level
Aerospace • Information Technology • Software • Cybersecurity • Design • Defense • Manufacturing
Develop and execute ASIC, FPGA, and SoC design verification activities using simulation, SystemVerilog, UVM, coverage analysis, debugging, requirements traceability, reusable verification infrastructure, and UVCs. Support integration and system-level investigations, contribute to coverage closure, communicate risks and dependencies, and progressively own verification scope of moderate complexity. Level II engineers develop independence, while Level III engineers independently manage assigned verification scope.
Top Skills: AsicFpgaOopRtlSimulationSocSystemverilogUvcUvm
54 Minutes Ago
In-Office
99K-162K Annually
Mid level
99K-162K Annually
Mid level
Aerospace • Information Technology • Software • Cybersecurity • Design • Defense • Manufacturing
Designs and supports ASIC, FPGA, and mixed digital systems for aerospace and defense programs. Responsibilities include requirements development, architecture support, HDL/RTL development, simulation, debugging, synthesis, FPGA implementation, timing analysis, verification collaboration, integration, troubleshooting, and technical status communication. The role may involve owning functional blocks, supporting subsystem efforts, and contributing to cross-functional technical leadership depending on experience level.
Top Skills: AsicClock-Domain Crossing (Cdc)FpgaHdlRtlSocStatic Timing AnalysisVlsi

What you need to know about the San Francisco Tech Scene

San Francisco and the surrounding Bay Area attracts more startup funding than any other region in the world. Home to Stanford University and UC Berkeley, leading VC firms and several of the world’s most valuable companies, the Bay Area is the place to go for anyone looking to make it big in the tech industry. That said, San Francisco has a lot to offer beyond technology thanks to a thriving art and music scene, excellent food and a short drive to several of the country’s most beautiful recreational areas.

Key Facts About San Francisco Tech

  • Number of Tech Workers: 365,500; 13.9% of overall workforce (2024 CompTIA survey)
  • Major Tech Employers: Google, Apple, Salesforce, Meta
  • Key Industries: Artificial intelligence, cloud computing, fintech, consumer technology, software
  • Funding Landscape: $50.5 billion in venture capital funding in 2024 (Pitchbook)
  • Notable Investors: Sequoia Capital, Andreessen Horowitz, Bessemer Venture Partners, Greylock Partners, Khosla Ventures, Kleiner Perkins
  • Research Centers and Universities: Stanford University; University of California, Berkeley; University of San Francisco; Santa Clara University; Ames Research Center; Center for AI Safety; California Institute for Regenerative Medicine

Sign up now Access later

Create Free Account

Please log in or sign up to report this job.

Create Free Account