Product Reliability Engineer

About the Team

OpenAI’s Hardware organization develops silicon and system-level solutions designed for the unique demands of advanced AI workloads. The team is responsible for building the next generation of AI-native silicon while working closely with software and research partners to co-design hardware tightly integrated with AI models. In addition to delivering production-grade silicon for OpenAI’s supercomputing infrastructure, the team also creates custom design tools and methodologies that accelerate innovation and enable hardware optimized specifically for AI.

The Compute team works on the design of our AI supercomputers, doing everything from workload modeling to influencing accelerator design. We’re leaning into our partnerships to make system and data center co-design an integral part of this process, and are looking for engineers to design AI supercomputers solutions for data center applications

This team is responsible for working with partners to optimize their hardware for our workloads, identifying promising new deep learning accelerators, and bringing those hardware platforms to production.

If you’re excited to work at the intersection of cutting edge deep learning, hardware system, and data center design this role is for you!

About the Role

We’re looking for a Product Reliability Engineer to own reliability engineering for advanced IT hardware, from printed circuit board assemblies (PCBAs) through compute and networking trays, systems, and fully integrated racks. You’ll translate operating conditions and service-life goals into reliability requirements, design and execute qualification tests, and drive failure analysis and corrective-action verification from development through production and field deployment. Working with electrical, mechanical, thermal, manufacturing, quality, and data center teams, suppliers, and manufacturing partners, you’ll use test and field evidence to improve hardware durability, serviceability, and availability.

This role is based in San Francisco, CA. We use a hybrid work model of 3 days in the office per week and offer relocation assistance to new employees.

In this role, you will:

• Define reliability requirements and targets for PCBAs, trays, systems, and racks using mission profiles, expected service life, operating environments, duty cycles, and availability goals.

• Drive design-for-reliability reviews with electrical, mechanical, and thermal engineers. Use failure modes and effects analysis (DFMEA or FMEA) and physics of failure to prioritize risks and recommend design improvements. Own component de-rating guidelines and guidance.

• Own reliability qualification plans from new product introduction through production, defining test coverage, representative configurations, sample sizes, stress conditions, duration, pass/fail criteria, and exit evidence at each assembly level.

• Develop and execute accelerated life and environmental tests, including temperature cycling, humidity exposure, power cycling, shock, vibration, and transport testing. Exercise hardware under representative workloads and monitor function and degradation during stress.

• Analyze life-test and field data using Weibull and other reliability models, acceleration models, and confidence intervals. State assumptions, exposure, and uncertainty when estimating failure rates, useful life, or reliability against targets.

• Lead failure investigations from symptom reproduction through physical root cause. Maintain failure reporting, analysis, and corrective-action records, and verify fixes through targeted testing and recurrence monitoring.

• Review supplier reliability plans and evidence for PCBs, PCBa components/assemblies, cables, connectors, and cooling components. Identify gaps between component qualification and the stresses encountered in the integrated system or rack.

• Work hands-on with internal and partner labs to develop fixtures, instrumentation, and test methods. Review sample traceability, test configurations, calibration, raw data, and failure capture, including on-site support at manufacturing partners.

• Partner with manufacturing and quality engineers to establish and validate reliability screens, burn-in where justified, and ongoing reliability testing. Confirm screening detects relevant defects without consuming unacceptable product life.

• Evaluate reliability risks introduced by assembly and integration: board strain and solder-joint damage, connector mating and retention, cable routing, fastener preload, power connections, and thermal interfaces. Partner with cooling specialists on leak integrity, material compatibility, corrosion, and cooling performance over life.

• Plan reliability test resources, lab capacity, hardware samples, schedules, and dependencies across programs with engineering teams, technical program managers, suppliers, and manufacturing partners.

• Present qualification results, unresolved failure modes, and residual risk at design and release reviews. Make evidence-based readiness recommendations and clearly identify test gaps, required follow-up, and decisions for accountable owners.

• Assess reliability impact and define targeted requalification for design, component, supplier, manufacturing process, and repair changes, including firmware changes that alter hardware operating stresses.

• Track field returns and fleet failure trends with service and data center teams. Correlate telemetry, failure analysis, and configuration history to prioritize corrective actions and feed lessons into future designs and qualification plans.

• Validate serviceability and repeated assembly or maintenance operations, including connector mating cycles and component replacement. Work with system engineers to assess how hardware failures, redundancy, and recovery affect rack availability.

You might thrive in this role if you:

• Have hands-on reliability engineering experience with advanced IT hardware, such as AI/HPC servers, networking equipment, or storage systems, spanning PCBAs, electromechanical assemblies, and integrated racks.

• Have designed, instrumented, and executed hardware reliability tests, debugged failures in the lab, and translated results into practical design or process improvements.

• Understand failure mechanisms in electronic assemblies, including solder fatigue, PCB and laminate damage, connector wear, corrosion, and thermal or mechanical degradation.

• Can turn mission profiles and failure risks into qualification plans, select defensible sample sizes and stress levels, and explain the assumptions and limits of accelerated testing.

• Have led reliability qualification through development and production milestones, balancing sample availability, lab capacity, schedule, and the evidence needed for release decisions.

• Have worked directly with component suppliers, joint design manufacturers, contract manufacturers, and external test labs to review test methods, resolve failures, and verify corrective actions.

• Apply design for reliability, DFMEA, and physics-of-failure methods across electrical, mechanical, and thermal interfaces, and understand how manufacturing, assembly, handling, and repair affect long-term reliability.

• Have driven structured failure analysis and corrective action using methods such as 8D, supported by electrical diagnostics, microscopy, X-ray, cross-section analysis, or specialist failure-analysis labs as appropriate.

• Can analyze reliability and life-test data, including censored data, Weibull distributions, and confidence bounds, using tools such as Python, R, JMP, or equivalent statistical software.

• Bring experience with high-power electronics, dense interconnects, or liquid-cooled hardware, including thermal interfaces, leak integrity, material compatibility, and serviceability.

• Communicate technical findings and uncertainty clearly, distinguish verified root cause and corrective-action effectiveness from hypotheses, and prioritize reliability risks when requirements or designs change.

To comply with U.S. export control laws and regulations, candidates for this role may need to meet certain legal status requirements as provided in those laws and regulations.

About OpenAI

OpenAI is an AI research and deployment company dedicated to ensuring that general-purpose artificial intelligence benefits all of humanity. We push the boundaries of the capabilities of AI systems and seek to safely deploy them to the world through our products. AI is an extremely powerful tool that must be created with safety and human needs at its core, and to achieve our mission, we must encompass and value the many different perspectives, voices, and experiences that form the full spectrum of humanity. 

We are an equal opportunity employer, and we do not discriminate on the basis of race, religion, color, national origin, sex, sexual orientation, age, veteran status, disability, genetic information, or other applicable legally protected characteristic.

For additional information, please see OpenAI’s Affirmative Action and Equal Employment Opportunity Policy Statement.

Background checks for applicants will be administered in accordance with applicable law, and qualified applicants with arrest or conviction records will be considered for employment consistent with those laws, including the San Francisco Fair Chance Ordinance, the Los Angeles County Fair Chance Ordinance for Employers, and the California Fair Chance Act, for US-based candidates. For unincorporated Los Angeles County workers: we reasonably believe that criminal history may have a direct, adverse and negative relationship with the following job duties, potentially resulting in the withdrawal of a conditional offer of employment: protect computer hardware entrusted to you from theft, loss or damage; return all computer hardware in your possession (including the data contained therein) upon termination of employment or end of assignment; and maintain the confidentiality of proprietary, confidential, and non-public information. In addition, job duties require access to secure and protected information technology systems and related data security obligations.

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