Design and validate mmWave RFIC front-end blocks for beamformer chips, including PAs, LNAs, phase shifters, VGAs, mixers, and transceiver chains. Responsibilities include transistor-level simulation, full-custom layout oversight, post-layout EM analysis, chip architecture, tapeout, silicon bring-up, characterization, debugging, documentation, and mentoring junior designers.
The Role
We’re looking for a Senior Staff RFIC Design Engineer to join the core design team. You’ll design, simulate, and validate mmWave front-end circuit blocks for our next-generation beamformer chips—including LNAs, PAs, phase shifters, VGAs, and complete transceiver signal chains.
This is a senior technical role with significant design ownership. You’ll work directly with the founding engineers, contribute to architecture decisions, and see your designs go from schematic to silicon to customer products.
Responsibilities
- Design mmWave front-end circuit blocks (PAs, LNAs, phase shifters, VGAs, mixers) in advanced CMOS or RFSOI (SiGe and III-V processes are a plus).
- Perform transistor-level schematic design, simulation, and optimization using Cadence Virtuoso (Spectre, ADE).
- Conduct full-custom IC layout or direct layout engineers, ensuring DRC/LVS-clean designs at mmWave frequencies.
- Perform post-layout extraction and EM simulation (Ansys HFSS, EMX, ADS Momentum) to validate performance through parasitics.
- Collaborate on chip-level architecture and system partitioning for multi-channel beamformer ICs.
- Support silicon bring-up, bench characterization, and debugging of fabricated chips.
- Contribute to tapeout preparation, design reviews, and documentation.
- Mentor junior RFIC designers and contribute to a culture of technical excellence.
Required Qualifications
- MS + 5 years industry experience or PhD + 2 years industry experience in Electrical Engineering with a focus on RF/mmWave IC design.
- Demonstrated expertise in at least two of: PA, LNA, phase shifter, VGA, mixer, or frequency multiplier design at mmWave frequencies.
- Expert proficiency with Cadence EDA suite (Virtuoso, ADE, and Layout) and EM simulation tools (Ansys HFSS, EMX, or ADS Momentum).
- Experience with at least one full tapeout cycle: schematic to layout to fabrication to bring-up to characterization.
- Strong understanding of mmWave transmission line theory, matching networks, and on-chip passive design.
- Track record of published work or shipped products demonstrating circuit design excellence.
Preferred Qualifications
- Experience with phased array or multi-channel beamformer IC design.
- Background in SATCOM, 5G NR FR2, or automotive radar mmWave applications.
- Experience in SOI nodes with high resistivity substrates.
- Familiar with system-level RF specs: EVM, P1dB, noise figure, IP3, EIRP, and G/T.
- Experience in a startup or small-team environment with high design ownership.
- Strong communication skills and ability to present design tradeoffs clearly.
Similar Jobs
Aerospace • Hardware • Semiconductor • Defense
Design and validate mmWave RFIC front-end blocks including PAs, LNAs, phase shifters, VGAs, and mixers. Perform transistor-level simulation, full-custom layout oversight, post-layout extraction, EM analysis, and chip-level architecture. Support tapeout, silicon bring-up, characterization, and debugging. Collaborate with founding engineers, contribute to design reviews and documentation, and mentor junior designers.
Top Skills:
AdeAds MomentumAnsys HfssCadence VirtuosoCmosDrcEmxIii-VLvsMmwave RficRfsoiSigeSpectre
Big Data • Cloud • Hardware • Software
Design high-performance analog and mixed-signal IC blocks at transistor, block, and module levels. Responsibilities include architecture, simulation, optimization, layout supervision, verification, test planning, characterization, reliability and yield assessment, bench-to-test correlation, and cross-functional communication.
Top Skills:
40Nm CmosAdcAnsysCadenceCmosDacFlash AdcLdoMentorOperational AmplifiersPmicSar AdcSiemens (Eda)
Big Data • Cloud • Hardware • Software
Design high-performance RF and analog IC blocks at transistor, block, and module levels. Responsibilities include architecture, simulation, optimization, layout supervision and verification, test-plan preparation, yield and reliability assessment, silicon bench evaluation, cross-functional communication, and documentation for mass-production releases.
Top Skills:
AdcAnsysBlock-Level RoutingCadenceCdrCmos (40Nm And Below)DacEm/Ir MitigationEqualizersFloorplanningHigh-Speed Drivers And ReceiversLnaMentor (Mentor Graphics)MixerPower AmplifierRficSiemens EdaSoa Mitigation
What you need to know about the San Francisco Tech Scene
San Francisco and the surrounding Bay Area attracts more startup funding than any other region in the world. Home to Stanford University and UC Berkeley, leading VC firms and several of the world’s most valuable companies, the Bay Area is the place to go for anyone looking to make it big in the tech industry. That said, San Francisco has a lot to offer beyond technology thanks to a thriving art and music scene, excellent food and a short drive to several of the country’s most beautiful recreational areas.
Key Facts About San Francisco Tech
- Number of Tech Workers: 365,500; 13.9% of overall workforce (2024 CompTIA survey)
- Major Tech Employers: Google, Apple, Salesforce, Meta
- Key Industries: Artificial intelligence, cloud computing, fintech, consumer technology, software
- Funding Landscape: $50.5 billion in venture capital funding in 2024 (Pitchbook)
- Notable Investors: Sequoia Capital, Andreessen Horowitz, Bessemer Venture Partners, Greylock Partners, Khosla Ventures, Kleiner Perkins
- Research Centers and Universities: Stanford University; University of California, Berkeley; University of San Francisco; Santa Clara University; Ames Research Center; Center for AI Safety; California Institute for Regenerative Medicine
