Etched Logo

Etched

RTL Design Engineer

Reposted Yesterday
Be an Early Applicant
In-Office
San Jose, CA, USA
150K-275K Annually
Senior level
In-Office
San Jose, CA, USA
150K-275K Annually
Senior level
The RTL Design Engineer will develop design verification strategies for ASIC designs, ensuring efficiency and performance of AI chips.
The summary above was generated by AI

About Etched

Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.

Job Summary

As an RTL Engineer at Etched, you will be critical in ensuring that our AI chips operate correctly and efficiently. You will develop and implement design verification strategies for both our existing and upcoming ASIC designs.

In this role, you will work closely with state-of-the-art architectures for machine learning. You do not need to have experience working with these yet, but you will be willing and able to learn quickly. You will work in a fast-paced environment with a high degree of autonomy, and be responsible for a key part of Etched’s success.

Representative projects

  • Implement a block to efficiently compute floating point math operators

  • Provide feedback to the uArch team to make sure blocks meet timing and area constraints

You may be a good fit if you

  • At least 5 years of work experience in RTL development.

  • Experience with high-speed digital logic.

  • Proficiency in standard RTL design and synthesis tools

  • Familiarity with verification work and writing test benches

  • Are able to learn quickly about transformers and other aspects of modern artificial intelligence

  • Willing to start quickly

Strong candidates may also have experience with (Nice-to-have qualifications)

  • Experience with PCIe, Ethernet, or HBM technologies

  • Familiarity with modern ML and LLM model architectures.

  • Familiarity with numerical representations and functions

  • ​Ability to program with Python or another scripting language

We encourage you to apply even if you do not believe you meet every single qualification.

Benefits

  • Medical, dental, and vision packages with generous premium coverage

    • $500 per month credit for waiving medical benefits

  • Housing subsidy of $2k per month for those living within walking distance of the office

  • Relocation support for those moving to San Jose (Santana Row)

  • Various wellness benefits covering fitness, mental health, and more

  • Daily lunch + dinner in our office

  • Unlimited compute budget subject to ROI justification

How we’re different:

Etched believes in the Bitter Lesson. We are the first inference-focused frontier AI system. Our addressable market is the entirety of inference, unlike many of our competitors.

 

We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both and work across disciplines as needed.

Similar Jobs

8 Days Ago
In-Office
121K-247K Annually
Mid level
121K-247K Annually
Mid level
Artificial Intelligence • Hardware • Information Technology • Machine Learning
Design and implement RTL for HBM SoC logic die, integrate internal and third-party IP, support SoC-level integration (clocking, reset, power intent), assist pre-/post-silicon validation and bring-up, and collaborate cross-functionally to meet performance, power, area, and manufacturability targets.
Top Skills: Agentic AiBiraBisrCadenceDramHardware EmulationHbmMbistPalladiumPerlPythonRtl-To-Gds FlowShell ScriptingSiemens EdaStatic Timing AnalysisSynopsysSynthesisSystemverilogTclVeloceVerilogZebu
6 Days Ago
In-Office
Sunnyvale, CA, USA
175K-275K Annually
Senior level
175K-275K Annually
Senior level
Artificial Intelligence • Hardware • Software • Semiconductor
Lead front-end RTL engineer responsible for functional specification, micro-architecture, RTL development, synthesis, and integration. Manage external ASIC vendors, collaborate with PD, verification, DFT, software and system teams, and debug silicon-level functional, timing, and power issues during bring-up to meet PPA and test coverage goals.
Top Skills: DftEthernetFloorplanningFpga Place And RoutePciePythonRdmaRtlSerdesSynthesisTclTcp/IpTiming Analysis
9 Days Ago
In-Office
Santa Clara, CA, USA
206K-251K Annually
Senior level
206K-251K Annually
Senior level
Software
Design and implement CPU microarchitecture features and ISA extensions using Chisel; integrate into Chisel/FIRRTL framework; perform sandbox verification and collaborate with verification, physical implementation, and performance teams to meet frequency, area, power, and performance goals. Produce documentation and participate in collaborative design.
Top Skills: ChiselFirrtlSystemverilogVerilogVhdl

What you need to know about the San Francisco Tech Scene

San Francisco and the surrounding Bay Area attracts more startup funding than any other region in the world. Home to Stanford University and UC Berkeley, leading VC firms and several of the world’s most valuable companies, the Bay Area is the place to go for anyone looking to make it big in the tech industry. That said, San Francisco has a lot to offer beyond technology thanks to a thriving art and music scene, excellent food and a short drive to several of the country’s most beautiful recreational areas.

Key Facts About San Francisco Tech

  • Number of Tech Workers: 365,500; 13.9% of overall workforce (2024 CompTIA survey)
  • Major Tech Employers: Google, Apple, Salesforce, Meta
  • Key Industries: Artificial intelligence, cloud computing, fintech, consumer technology, software
  • Funding Landscape: $50.5 billion in venture capital funding in 2024 (Pitchbook)
  • Notable Investors: Sequoia Capital, Andreessen Horowitz, Bessemer Venture Partners, Greylock Partners, Khosla Ventures, Kleiner Perkins
  • Research Centers and Universities: Stanford University; University of California, Berkeley; University of San Francisco; Santa Clara University; Ames Research Center; Center for AI Safety; California Institute for Regenerative Medicine

Sign up now Access later

Create Free Account

Please log in or sign up to report this job.

Create Free Account