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Lattice Semiconductor

Senior Analog IC Design Engineer

Posted 8 Days Ago
Be an Early Applicant
In-Office
San Jose, CA, USA
211K-211K Annually
Senior level
In-Office
San Jose, CA, USA
211K-211K Annually
Senior level
Designs and develops analog and mixed-signal IC circuit blocks from specification and architecture through post-silicon verification. Responsibilities include circuit simulation, physical design coordination, integration into complex digital chips, bench-level test planning, characterization, debugging, and mentoring junior engineers. The role requires advanced analog circuit expertise, FinFET design experience, and proficiency with Cadence AMS tools and methodologies.
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Lattice Overview

There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.

Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.

Job Description:

We are looking for a Senior Analog IC Design Engineer to join our team. This person is responsible for the design and development of analog, mixed-signal IC circuit blocks from initial specification and architecture to final, post-silicon verification to ensure specifications are met.

Responsibilities include:

  • Analog, mixed-signal circuit design and simulation

  • Work with mask designers to deliver physical design

  • Integration of analog/mixed-signal blocks into large, complex, digital chips

  • Define bench-level test plans for post-silicon characterization and debug

  • Lead/mentor junior engineers

Qualifications:

  • BS, MS, and/or PhD in Electrical Engineering or related fields

  • Multiple years of experience working in analog/mixed-signal circuit design (BSEE, 10+ years, MS 8+ years, PhD 5+ years)

  • Proven design experience in most of the following analog, mixed-signal circuits: SerDes receivers/transmitters, low-jitter PLLs, oscillators, phase interpolators, ADC/DAC, high speed clock distribution, bandgap/bias, and voltage regulators

  • In-depth knowledge of transistor mismatch, linearity, stability, low-power and low-noise techniques

  • Experience designing circuits in advanced FinFET technologies

  • Proficient in AMS design flows, tools, and methodologies like Cadence schematic capture, Virtuoso, Spectre, layout, and analog behavioral modeling

  • Detailed oriented, with excellent problem-solving skills, communication skills, and the ability to work collaboratively in a fast-paced, team environment

Pay & Benefits

Consistent with Lattice Semiconductor values and applicable law, we provide the following information to promote pay transparency and equity. We have a market-based pay structure which varies by location.  Please note that the base pay range is a guideline, and our compensation range reflects the cost of labor in the U.S. geographic market based on the location of the role. Pay within these ranges varies and depends on job-related knowledge, skills, and relevant work experience. 

For candidates who receive and offer, the starting salary will vary based on various factors including, but not limited to, such qualifications as, skill level, competencies, and work location.  The range provided may represent a candidate range and may not reflect the full range for an individual tenured employee.

Base Pay Range

211200

In addition to base pay, this role may be eligible for variable/ incentive compensation and/ or equity.  In addition, this role is eligible for a comprehensive, competitive benefits package which may include healthcare and retirement plans, paid time off, and more! 

Additional Information:

This position requires a successful background and reference checks and satisfactory proof of your right to work in the United States.

Lattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. 


Lattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit 
www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.

 

As an E-Verify employer, we use this system to confirm the employment eligibility of all new hires in accordance with federal law. All applicants will be required to complete a Form I-9, Employment Eligibility Verification, upon hire. We do not use E-Verify to pre-screen job candidates and will comply with all E-Verify regulations.

Lattice Semiconductor San Jose, California, USA Office

2115 Onel Dr, San Jose, CA, United States, 95131

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