Implement and verify DFT solutions for complex SoC and ASIC designs across scan, compression, ATPG, JTAG, boundary scan, MBIST, memory repair, hierarchical DFT, simulation, timing constraint debugging, silicon bring-up, and tape-out activities. The role requires Siemens Tessent expertise, scripting in TCL or Perl, strong debugging skills, and successful advanced-node design experience.
Senior DFT Engineer | California (Onsite)
We are looking for a Senior DFT Engineer to support the implementation and verification of DFT solutions for complex SoC/ASIC designs. The ideal candidate will have hands-on experience across the full DFT flow, from scan implementation through ATPG, MBIST, and silicon bring-up activities.
Key Requirements:
- 3 to 8 years of experience in DFT for SoC/ASIC designs
- Strong experience with Scan, Compression, ATPG, JTAG, and Boundary Scan
- Hands-on experience with MBIST implementation, verification, and Memory Repair (BIRA/BISR)
- Experience with hierarchical SoC DFT implementation and verification
- Familiarity with DFT simulations, SDF timing simulations, and debugging timing constraints
- Experience with industry-standard DFT tools such as Siemens Tessent, Synopsys, or Cadence tool suites
- Scripting skills in TCL and/or Perl
- Experience with successful SoC/ASIC tape outs, preferably at advanced technology nodes (5nm or below)
- Strong debugging, problem-solving, communication, and teamwork skills
- Experience with Tessent EDA tools is a must
Location: Bay Area, CA
Work Authorization: Green Card & US citizens
Employment Type: 1099 contract.
MosChip Santa Clara, California, USA Office
4699 Old Ironsides Dr Ste 270, Santa Clara, United States, 95054
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