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NVIDIA

Senior Director, Board Product Development Engineering

Posted One Month Ago
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In-Office
Santa Clara, CA, USA
332K-500K Annually
Senior level
In-Office
Santa Clara, CA, USA
332K-500K Annually
Senior level
Lead and build a global Board Product Development Engineering organization to ensure chip-to-board integration readiness, manufacturing/test readiness, and yield for next-generation datacenter boards. Define cross-domain gates, drive DFM and SI practices, collaborate with suppliers and operations, investigate yield excursions, and own schedule, quality, and reliability through NPI to high-volume manufacturing.
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NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world.

NVIDIA’s advanced datacenter boards push forward chip packaging, PCB fabrication, SMT, assembly, and testing capabilities. Dedicated teams take responsibility for each technology: packaging manages the package, PCB and materials handle fabrication and stack-up, SMT and assembly oversee build processes, and test and SI focus on test capabilities. The challenge is to align these improvements across the stack—from chip to PCB, PCB to SMT, SMT to assembly, and assembly to test. Each domain’s innovation delivers maximum benefit when downstream consequences are considered early. The Senior Director, Board PDE oversees integration methods that make this possible—coordinating handoffs, engineering cross-domain effects before changes, and optimizing the entire chain.

What you'll be doing:

  • Design, implement, and institutionalize the integration readiness process for all next-generation datacenter board products — owning manufacturing and test readiness end to end so build starts land on schedule and at target yield.

  • Guide the functional teams in developing cross-boundary techniques before silicon and stackup freeze occurs. Focus on warpage-tolerant DFM and reflow for next-gen BGA pitch. Manage impedance and CTE control for high-speed stackups. Lock pad-map and fab methods at an early stage.

  • Build, lead, and develop a global Board PDE organization across three technical pillars — PCB & Fab, SMT/PCBA, and High-Speed Connector & Signal Integrity.

  • Set up integration oversight throughout the chip-to-board stack. Define entry and exit requirements at each domain boundary. Lead the gates to confirm one qualified domain is ready to pass to the next.

  • Collaborate with Operations Test Engineering and Signal Integrity to establish test coverage and manufacturing test flow requirements, applying that thoroughness to the tester and diagnostic boards.

  • Take charge of reliability and yield performance throughout the stack. Investigate excursions to identify root causes. Address DFx and alternate-component gaps with the factory planning and design teams.

  • Support manufacturing partners (CM/ODM/OSAT, substrate, and PCB fab) in producing world-class datacenter products. Serve as the senior chip-to-board representative across NVIDIA's Operations, Engineering, and Executive teams.

What we need to see:

  • BS in Electrical Engineering, Materials Science, or a related technical field (or equivalent experience); MS or PhD is a plus.

  • 15+ overall years in product, manufacturing, or operations engineering for high-complexity electronics. You have 8+ years leading engineering teams and 5+ years leading leaders in a global, cross-matrixed organization.

  • A track record of taking complex board and system products from design through NPI to high-volume manufacturing, with clear ownership of schedule, yield, and quality outcomes.

  • Comprehensive technical knowledge covering the chip-to-board stack: advanced packaging and flip-chip BGA, high-density and high-layer-count PCB fabrication, SMT and assembly process qualification, and board-level reliability.

  • Solid expertise in high-speed signal integrity and manufacturing testing — BERT, channel margining, defining structural and functional test coverage, along with diagnostic and tester board development.

  • Demonstrated success building cross-functional processes and sign-off gates that hold up under schedule pressure, with the technical credibility to influence domain owners without owning their qualification.

  • Experience collaborating with ODM/CM/OSAT and PCB fab suppliers to qualify new methods before production, rather than just completing existing ones.

  • Excellent executive communication — able to distill ambiguous, fast-moving technical information into concise, decision-ready recommendations for technical and non-technical audiences alike.

  • Enthusiasm for fast-paced, ambiguous environments where technology changes constantly, and willingness to travel internationally (~20%), primarily to manufacturing partners in Asia.

Ways to stand out from the crowd:

  • Full accountability for board manufacturing processes and yields on AI or datacenter platforms at hyperscale.

  • Depth in next-gen interconnect and packaging — 112G/224G SerDes correlation, fine-pitch BGA, 2.5D/3D packaging — taken through assembly into HVM at healthy first-pass yield.

  • A track record of validating new materials, fabrication technologies, and board manufacturing processes into high-volume manufacturing before the industry standard.

  • Proven board-level yield improvement: defect baselines, process-to-yield correlation, and systemic excursions driven to permanent corrective action.

  • Success scaling a technical organization from a small core into a global, multi-site team.

With competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us. This role presents an opportunity to have a wide impact at NVIDIA by improving the factory planning function. Are you creative, hard-working, dedicated, and determined? Do you love a challenge? If so, we want to hear from you!

As you plan your future, see what we can offer to you and your family www.nvidiabenefits.com/

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 332,000 USD - 500,250 USD.

You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until August 21, 2026.

This posting is for an existing vacancy. 

NVIDIA uses AI tools in its recruiting processes.

NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

HQ

NVIDIA Santa Clara, California, USA Office

2701 San Tomas Expressway, Santa Clara, CA, United States, Santa Clara

NVIDIA San Francisco, California, USA Office

San Francisco, United States

NVIDIA San Jose, California, USA Office

San Jose, United States

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