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Intel

Senior Power and Performance Engineer

Posted Yesterday
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In-Office
Santa Clara, CA, USA
142K-200K Annually
Senior level
In-Office
Santa Clara, CA, USA
142K-200K Annually
Senior level
Measure, analyze, and debug power and performance of Intel and competitor SoC/CPU platforms on Linux and Android/Chromebook. Create rail-by-rail power measurements, develop projections/estimates for unlaunched products, bring up test platforms, align with internal teams, and influence OEMs and marketing for product launches.
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Job Details:

Job Description: 

Note: This role requires regular onsite presence to fulfill essential job responsibilities.
Job Description: As a Senior Power and Performance (PnP) Engineer, you will be responsible for PnP product execution focused on measurements, analysis, and projections/estimates of Intel's unlaunched products and competitor products. Based on your technical knowledge of both Intel and the competition, you will help influence OEM customers, internal marketing teams, internal engineering teams, debug Intel silicon/platform on PnP issues, and be an integral part for Intel product launches.
This role is for Santa Clara on-site everyday (no remote/no hybrid option).
Core responsibilities to include following:
- Measure, analyze, and debug workloads to call out any power and/or performance gaps on Linux and Android/Chromebooks.
- Measure and analyze SoC/CPU and platform power on a rail by rail basis and debug any issues/gaps
- Align with other internal engineering teams and architects to ensure there is consensus on power and performance projections/estimates/measurements for both internal and external communication
- Guide, educate, and influence internal engineering teams, field account teams, and marketing teams on power and performance positioning of Intel products
- Create power and performance estimates on upcoming Intel products based on workloads to aid marketing decisions and help set internal KPI targets
- Bring up full test platform to enable both power and performance measurements including setup, calibration, and measurements.

Qualifications:

Minimum Qualifications:
- Bachelor's/Master's (BS/MS) in Computer Engineering / Electrical Engineering / Computer Science with at least 2 years of experience

Either/Or in the below:
- Prior experience in a post-silicon environment
- Prior experience working in a Linux, Android, or Chromebook test environment
Preferred Qualifications:
- Bachelor's/Master's (BS/MS) in Computer Engineering / Electrical Engineering / Computer Science with 3 to 8 years of experience
- Understanding of standard benchmarks and ability to analyze performance
o Familiarity with industry benchmarks is a plus (ie SPEC CPU, Speedometer, Geekbench, MLPerf, Passmark, Antutu)
- Experience with Linux or Android/Chromebook debug tools
- Attention to detail and ability to analyze data for accuracy/trends
- Strong knowledge of CPU micro-architecture (knowledge of x86 or ARM CPU uarch added plus)
- Familiarity with ITP/JTAG scripts, board bring up, power measurements with DAQ
- Prior experience with Intel products or other CPU products in a post-silicon engineering environment
- Excellent verbal and written communication skills - Experience developing customized content for a technical audience

          

Job Type:Experienced Hire

Shift:Shift 1 (United States of America)

Primary Location: US, California, Santa Clara

Additional Locations:

Business group:Intel makes possible the most amazing experiences of the future. You may know us for our processors. But we do so much more. Intel invents at the boundaries of technology to make amazing experiences possible for business and society, and for every person on Earth. Harnessing the capability of the cloud, the ubiquity of the Internet of Things, the latest advances in memory and programmable solutions, and the promise of always-on 5G connectivity, Intel is disrupting industries and solving global challenges. Leading on policy, diversity, inclusion, education and sustainability, we create value for our stockholders, customers, and society.

Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.



Annual Salary Range for jobs which could be performed in the US: $141,910.00-200,340.00 USD

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

*

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
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Robert Noyce Building, Santa Clara, CA, United States, 95052

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Mountain View, United States

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San Jose, United States

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2200 Mission College Blvd. , Santa Clara, CA, United States, 95054

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Sunnyvale, United States

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