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NVIDIA

Senior Product Development Engineer - Datacenter Boards

Posted 4 Days Ago
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In-Office
Santa Clara, CA, USA
136K-259K Annually
Senior level
In-Office
Santa Clara, CA, USA
136K-259K Annually
Senior level
Leads new product introduction for datacenter and HPC boards from first article through mass production. Develops manufacturing test strategies, analyzes yield and manufacturing data, performs root-cause analysis across silicon, PCB, firmware, and system layers, and drives DFM/DFT improvements. Collaborates with engineering, operations, suppliers, and contract manufacturers worldwide while communicating quality, yield, risk, and delivery status to leadership. Travel up to 15% is required.
The summary above was generated by AI

We build the hardware that runs the world's AI — and our Operations NPI team is how we bring it from silicon to data center at scale. At NVIDIA, we're proud to work on GPU platforms like Blackwell and Vera Rubin that push the boundaries of what's possible in compute. We move fast, we care deeply about quality, and we invest in people who want to grow across disciplines — board design, test engineering, yield analytics, and global manufacturing, often within a single program cycle. If you're energized by complex hardware challenges and want to see your work running inside the world's most powerful AI infrastructure, we'd love to talk.

What you'll be doing:

  • Module and board NPI for datacenter and HPC products is the core of this role — from first-article through mass production ramp, with accountability for yield targets, quality gates, and on-time delivery. We work closely across Engineering, Mechanical, Thermal, Program Management, and Operations to surface risks early and keep programs on track.

  • Our team defines and continuously improves manufacturing test plans — balancing coverage, test-time, cost, and yield across board and system levels — and we partner with CM sites worldwide to qualify and scale those solutions. We analyze volume manufacturing data using scripting and analytics tools to surface trends that matter and translate them into decisions quickly.

  • When boards fail, we go deep — root-cause analysis across silicon, PCB, and system layers, with findings turned into concrete DFM and DFT improvements for design teams. We hold ourselves and our suppliers to high engineering and quality standards, and we brief leadership regularly on status, yield trends, and improvement roadmaps.

What we need to see:

  • 5+ years in product engineering, product development, manufacturing, or validation of PCBs, silicon, or complex systems experience.

  • Hands-on depth in two or more of the following: server architectures and datacenter system integration; PCB/board design, SMT, and assembly process engineering; board-level or post-silicon validation and characterization; high-speed interface validation (PCIe, NVLink, Ethernet, PAM4); Power Integrity analysis and thermal characterization; or complex test setup design and automation.

  • History of leading complex GPU or board-level projects to mass production on schedule, with high quality and yield.

  • Ability to diagnose and resolve multi-disciplinary problems spanning silicon, board, firmware, and system layers.

  • Clear understanding of testing strategy economics — how coverage, test-time, and escape rate relate to yield and cost outcomes.

  • Communicates complex technical data clearly to both engineering and business audiences.

  • Travel Requirement: Willingness to travel up to 15%, both domestically and internationally.

  • Bachelor’s degree in Electrical Engineering or Master's degree in Electrical Engineering, or equivalent experience.

Ways to stand out from the crowd:

  • Python or scripting experience applied to manufacturing analytics, test automation, or data pipelines.

  • Background coordinating cross-functional debug efforts across silicon, board, and systems.

  • Familiarity with HPC and hyperscale datacenter requirements — hardware engineering, power, cooling, reliability, and serviceability.

  • Experience qualifying advanced memory solutions (HBM, LPDDR) or high-speed SerDes interfaces.

  • Knowledge of PCBA manufacturing processes, mechanical tolerances, and system-level assembly constraints.

Your base salary will be determined based on your location, experience, and other objective job-related factors. The expected base salary ranges for this position are:
136,000 USD – 212,750 USD for Level 3; and 168,000 USD – 258,750 USD for Level 4.

You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until November 3, 2026.

This posting is for an existing vacancy. 

NVIDIA uses AI tools in its recruiting processes.

NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

HQ

NVIDIA Santa Clara, California, USA Office

2701 San Tomas Expressway, Santa Clara, CA, United States, Santa Clara

NVIDIA San Francisco, California, USA Office

San Francisco, United States

NVIDIA San Jose, California, USA Office

San Jose, United States

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