Microsoft Logo

Microsoft

Senior Silicon Design Verification Engineer

Reposted 5 Days Ago
Be an Early Applicant
In-Office
Mountain View, CA, USA
120K-261K Annually
Senior level
In-Office
Mountain View, CA, USA
120K-261K Annually
Senior level
Design and run C/C++ firmware-style tests and extend build flows; own FPGA prototyping platforms and create board images/RTL; build Python tooling; perform FPGA and post-silicon lab bring-up and debug using JTAG, logic analyzers, oscilloscopes; root-cause failing tests, analyze scan dumps, coordinate cross-team fixes, and deliver validation signoff.
The summary above was generated by AI
Overview

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission.

The Compute Silicon & Manufacturing Engineering (CSME) organization within SCHIE is responsible for design, development, manufacturing and packaging of Microsoft's state-of-the-art computer chips, notably the Azure Cobalt. Our solutions provide sustainable strategic advantage to Microsoft and enable our customers to achieve more.

As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the Shared and Custom IP & Silicon (SCIPS) team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure.

 We are looking for a Senior Silicon Design Verification Engineer to join the team.


#SCHIE #CSME


Responsibilities

The candidate for this position will be expected and able to complete the following responsibilities:

  • Develop C and C++ based test content, low-level drivers, and custom firmware at the subsystem and SoC levels, including self-checking tests that run on embedded processors.
  • Extend the compile and build flow to support custom firmware-style tests.
  • Serve as a technical owner for the team's FPGA prototyping platforms (such as HAPS or Xilinx): create board images and bit files. Design additional custom FPGA RTL for protocol interfaces and feature enablement. Release stable platforms to the firmware team and keep them working as the design evolves.
  • Develop and extend custom python tooling to interface with the FPGA platform.
  • Debug FPGA and post-silicon issues using tools such as JTAG debuggers, logic analyzers, oscilloscopes, and multimeters
  • Drive post-silicon bring-up and validation in the lab: run the validation suites on first silicon, meet bring-up exit criteria on schedule, and debug platform issues such as JTAG failures, UART connectivity, and boot failures alongside the design, firmware, hardware, and security teams.
  • Root-cause failing post-silicon tests to closure, collecting and analyzing scan dumps for low-level issues such as boot ROM and built-in self-test bugs, coordinating cross-team debug, and delivering fixes such as handling fatal errors, correcting driver access violations, and reconciling registers modified by boot firmware.

Qualifications

Required Qualifications:

  • Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience
    • OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience
    • OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience
    • OR equivalent experience. 

Preferred Qualifications:

  • Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience.
  • Experience developing C and C++ test content for subsystem and SoC verification, including bare-metal and firmware-style tests, with working knowledge of SystemVerilog testbenches.
  • Experience bringing up and maintaining FPGA prototyping or emulation platforms (such as HAPS or Xilinx), including board images, platform tooling, and testbench changes that enable firmware and validation teams.
  • Hands-on hardware debug experience with tools such as JTAG debuggers, logic analyzers, oscilloscopes, and multimeters
  • Experience owning pre-silicon verification of IP, subsystems, or SoCs through the full cycle, including test planning, test development, failure debug, and coverage signoff.
  • Experience with post-silicon bring-up and validation, including running test suites on silicon and debugging boot, platform, and connectivity issues in a lab environment.
  • Proficiency in Python, or a similar scripting language such as Perl or Ruby, for test automation, build flows, and log or data parsing.
  • In-depth knowledge of verification principles, testbench architecture, and stimulus generation, with a track record of debugging complex designs.
  • Experience with low-level and embedded software, including assembly, startup code, linker scripts, and Makefile-based build flows.
  • Familiarity with industry protocols such as AMBA (AXI/AHB/APB), JTAG, SPI, I2C/I3C, and USB.
  • Experience collaborating across architecture, design, firmware, and validation teams, with strong communication skills.
  • Understanding of silicon and/or computer architecture.

Screening Requirements

  • Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
  • This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations.  As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.


Silicon Engineering IC4 - The typical base pay range for this role across the U.S. is USD $119,800 - $234,700 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $160,200 - $261,000 per year.

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:
https://careers.microsoft.com/us/en/us-corporate-pay


This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.



Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.

Microsoft Mountain View, California, USA Office

1065 La Avenida, Mountain View, CA 94043, Mountain View, United States, 94043

Microsoft Palo Alto, California, USA Office

Palo Alto, United States

Microsoft San Francisco, California, USA Office

835 Market Street, Suite 700, San Francisco, CA 94103, San Francisco, United States, 94103

Microsoft San Jose, California, USA Office

San Jose, United States

Microsoft Sunnyvale, California, USA Office

Sunnyvale, United States

Similar Jobs

One Month Ago
In-Office
165K-260K Annually
Senior level
165K-260K Annually
Senior level
Aerospace • Other
Lead digital ASIC verification at block and system levels: write and review test plans, develop test harnesses and sequences, run regressions and close code/functional coverage, and support pre-silicon verification, chip bring-up, and post-silicon validation for complex digital designs.
Top Skills: AsicCode CoverageConstrained Random VerificationFunctional CoverageObject-Oriented ProgrammingOvmPythonRtlTestbench DevelopmentUvmVmm
One Month Ago
In-Office
Palo Alto, CA, USA
175K-280K Annually
Senior level
175K-280K Annually
Senior level
Aerospace • Other
Lead digital ASIC verification at block and system levels: author and execute test plans, develop test harnesses and regressions, drive coverage closure, support pre-silicon verification, chip bring-up and post-silicon validation, and collaborate with cross-disciplinary teams to verify complex designs.
Top Skills: AsicCode CoverageConstrained-Random VerificationFunctional CoverageOvmPythonRtlTestbenchUvmVmm
Entry level
Software • Hospitality
Prepares menu items and guest orders according to recipes and quality standards. Performs basic food preparation and cooking, inspects dishes for presentation, maintains stocked and sanitary workstations, operates kitchen equipment, and follows food handling, health, safety, sanitation, and alcohol awareness regulations.

What you need to know about the San Francisco Tech Scene

San Francisco and the surrounding Bay Area attracts more startup funding than any other region in the world. Home to Stanford University and UC Berkeley, leading VC firms and several of the world’s most valuable companies, the Bay Area is the place to go for anyone looking to make it big in the tech industry. That said, San Francisco has a lot to offer beyond technology thanks to a thriving art and music scene, excellent food and a short drive to several of the country’s most beautiful recreational areas.

Key Facts About San Francisco Tech

  • Number of Tech Workers: 365,500; 13.9% of overall workforce (2024 CompTIA survey)
  • Major Tech Employers: Google, Apple, Salesforce, Meta
  • Key Industries: Artificial intelligence, cloud computing, fintech, consumer technology, software
  • Funding Landscape: $50.5 billion in venture capital funding in 2024 (Pitchbook)
  • Notable Investors: Sequoia Capital, Andreessen Horowitz, Bessemer Venture Partners, Greylock Partners, Khosla Ventures, Kleiner Perkins
  • Research Centers and Universities: Stanford University; University of California, Berkeley; University of San Francisco; Santa Clara University; Ames Research Center; Center for AI Safety; California Institute for Regenerative Medicine

Sign up now Access later

Create Free Account

Please log in or sign up to report this job.

Create Free Account