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SiFive

Software Engineer - FPGA-Accelerated RTL Simulation

Posted 12 Hours Ago
Be an Early Applicant
In-Office
Berkeley, CA, USA
179K-219K Annually
Senior level
In-Office
Berkeley, CA, USA
179K-219K Annually
Senior level
Develop and maintain the high-performance C++ application for an FPGA-hosted hardware emulation framework. Collaborate with FPGA RTL designers, compiler developers, and RISC-V engineers to enable fast, debuggable, and cost-effective emulation for software and hardware co-design.
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About SiFive

As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.

At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.  

Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions.  Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time. 

Are you ready?  

To learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.

Job Description:

 

The Role

You will be responsible for the C++ application that constitutes the software-component of our custom hardware emulation framework (originally based on FireSim, https://fires.im). Join a small team (<5 engineers) working on a cross-cutting project that spans the whole stack. You will work closely with:

  • FPGA RTL Designers: Components of our FPGA-hosted emulators are written in Chisel and optimized for Xilinx FPGAs.

  • Compiler Developers: We compile ASIC RTL down to deterministic, FPGA-friendly emulation RTL using a purpose-built compiler based on MLIR & CIRCT.

  • RISC-V Software & HW Developers: Build debug tools to help users co-design and debug novel RISC-V hardware and software.

Your experience should be rooted in high-performance, multithreaded C++ application development. Familiarity with compiler development (ideally LLVM or MLIR) or FPGA RTL design is highly desired, but not required.

You will help build the next generation of hardware emulation capacity for our RISC-V core IP—making it fast for software development, productive to debug, and cost-effective for deployment to every engineer in the company.

Requirements:

  • BS/MS/PhD in CS, CE, or EE.

  • 7+ years experience building complete C++ applications, using modern C++ language features and best practices (C++20 and newer).

  • Strong understanding of C++ concurrency features and demonstrated experience building multithreaded applications.

  • Self-directed, with strong oral and written communication skills.

Pay & Benefits

Consistent with SiFive values and applicable law, we provide the following information to promote pay transparency and equity. We have a market-based pay structure which varies by location.  Please note that the base pay range is a guideline, and our compensation range reflects the cost of labor in the U.S. geographic market based on the location of the role. Pay within these ranges varies and depends on job-related knowledge, skills, and relevant work experience. 

For candidates who receive and offer, the starting salary will vary based on various factors including, but not limited to, such qualifications as, skill level, competencies, and work location.  The range provided may represent a candidate range and may not reflect the full range for an individual tenured employee.

Base Pay Range

$178,848.00-$218,592.00

In addition to base pay, this role may be eligible for variable/ incentive compensation and/ or equity.  In addition, this role is eligible for a comprehensive, competitive benefits package which may include healthcare and retirement plans, paid time off, and more! 

Additional Information:

This position requires a successful background and reference checks and satisfactory proof of your right to work in

United States of America

Any offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.

SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.

As an E-Verify employer, we use this system to confirm the employment eligibility of all new hires in accordance with federal law. All applicants will be required to complete a Form I-9, Employment Eligibility Verification, upon hire. We do not use E-Verify to pre-screen job candidates and will comply with all E-Verify regulations.

California residents: please see our job candidate notice for more information on how we handle your personal information and your privacy rights: Privacy Policy Document.

HQ

SiFive Santa Clara, California, USA Office

Santa Clara, CA, United States

SiFive Berkeley, California, USA Office

2000 Hearst, Suite 400, Berkeley, CA, Berkeley, United States, 94709

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