We are looking for engineers with strong algorithmic foundations and a passion for building highly scalable C/C++ solutions to work on the core Static Timing Analysis (STA) engine.
The role involves designing, tuning, and innovating timing and graph algorithms operating on multi‑billion‑node timing graphs. These scale challenges require highly distributed, incremental, and parallel solutions, including opportunities to leverage GPU acceleration for performance‑critical workloads.
At advanced technology nodes, incorporating device variation and statistical modeling into the timing engine introduces additional complexity. Candidates with experience or strong interest in statistical timing, variation modeling, or large‑scale numerical algorithms are preferred.
Qualifications
- Strong background in algorithms, data structures, and graph theory
- Proficiency in C/C++ and performance‑oriented system design
- Interest or experience in distributed systems, parallel computing, or GPU acceleration
- Exposure to STA, EDA, or digital design concepts is a plus
- Strong communication and teamwork skills
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The annual salary range for California is $114,800 to $213,200. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
We’re doing work that matters. Help us solve what others can’t.Cadence Design Systems San Jose, California, USA Office
2655 Seely Avenue, San Jose, CA, United States, 95134
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