DV - Digital Verification Engineer (Senior levels - Staff +)

Key Responsibilities:

• Develop and execute verification plans for connectivity IPs and Chiplets
• Create and maintain SystemVerilog/UVM-based verification environments
• Write and debug SystemVerilog/UVM compliant test cases for block and chip level
• Maintain a regression environment for enabling design CI/CD pipelines
• Collaborate with design engineers to ensure design quality with continuous microarchitecture, test-plan, and coverage reviews
• Develop, maintain, and track various test plan items and progress towards RTL freeze
• Stay up to date with industry trends, emerging technologies and progress in standards’ bodies
• Ensure IP compliance with Ethernet standards (IEEE 802.3)
• Integration 3rd party VIPs and coordinate feature/bug tracking requests
• Perform in the capacity of a technical leader for junior verification engineers
• Create, improve, maintain DPI based FW simulation environments
• Create, improve, maintain GLS environments for functional and power simulations

Qualifications:

• Masters or Ph.D in Electrical Engineering and related fields with 6+ years of experience
• Hands on experience in verification of serial transmission protocols and products (preferably in retimer, gearbox, Ethernet PMA/PCS logic)
• Strong expertise in UVM, test environment and assertion coding with SystemVerilog
• Proficiency in 3 rd party tools for regression management and coverage analysis
• 3+ experience working on Ethernet 802.3 standards’ clauses related to 100G, 200G, 400G, 800G; Auto-Negotiation and Link Training
• Knowledge of DRAM Controllers/PHYs and HBM Memory a plus
• Strong bias for innovations across all aspects of digital verification including automation of mundane activities and methods for quality improvement
• Experience in verifying 3 rd party mixed signal IPs as well as integration of VIPs
• Proven track record of being part of a start-up like environment