As a Senior Staff Physical Design Engineer, you'll oversee ASIC design processes from RTL to GDSII, ensuring high-quality delivery and optimizing design flows in a startup environment.

Lead and manage physical design teams, execute design strategy, optimize ASIC design flows, collaborate with cross-functional teams, and ensure successful tapeout.

Lead global positioning and go-to-market strategies for connectivity products in AI data centers, emphasizing high-speed low-latency technologies.

As a Signal and Power Integrity Engineer, you'll develop packaging solutions for chiplet interconnects, optimizing performance through simulation, measurement, and collaboration with cross-functional teams.

Design and develop complex PCBs for chiplet products, optimize power systems, implement high-speed interfaces, and collaborate with manufacturers.

Lead ASIC and platform development, manage cross-functional teams, oversee project timelines, budgets, and vendor relationships to ensure successful program delivery.