Staff Physical Design Engineer, HBM

Our vision is to transform how the world uses information to enrich life for all .
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
Responsibilities will include, but are not limited to:

• Drive end-to-end physical design for HBM base die and/or memory dies from netlist through GDSII.
• Own floorplanning, power planning, placement, CTS, routing, and signoff for HBM designs with very high macro density.
• Define and drive HBM-specific physical architecture, including channel partitioning, PHY placement, and TSV keep-out regions.
• Work with design to make architecture-level tradeoffs to optimize bandwidth, latency, power, and yield.
• Assist power delivery network (PDN) design for extremel high current density environments.
• Drive IR drop, EM, and thermal closure across all operating modes.
• Ensure compliance with foundry reliability rules, including EM lifetime, via density, and TSV stress considerations.
• Own timing closure across corners for high-speed internal logic and HBM PHY interfaces.
• Partner with clocking and PHY teams on clock distribution, skew control, and jitter sensitivity.
• Collaborate with packaging teams on 2.5D interposer-based integration and HBM stack interfaces.
• Ensure physical alignment of micro-bumps, TSVs, RDLs, and keep-out zones.
• Own physical signoff readiness: STA, IR/EM, SI, DRC, LVS, density, and reliability.
• Bringing to bear AI in LVS/DRC fix automation throughout the build phase.
• Lead ECO strategies, including late-stage timing and power fixes.
• Act as a key technical voice in tape-out and executive design reviews.
• Partner with memory design, PHY, RTL, synthesis, DFT, SI, packaging, and test teams.
• Influence memory architecture and interface definitions to improve physical feasibility.
• Mentor senior and developing engineers; establish HBM-specific PD guidelines and methodology.
• Drive flow improvements, automation, and reuse across HBM generations.

HOW TO QUALIFY

• Bachelor's degree or Master's degree or equivalent experience in Electrical Engineering, Computer Engineering, or a related field.
• 7+ years of hands-on experience in advanced-node physical design.
• Proven tape-out experience on HBM, DRAM, or very large memory-centric designs.
• Deep expertise in:
• Floorplanning and hierarchical, PDTiming closure and STA fundamentals, power integrity (IR/EM) and thermal awareness, physical signoff for advanced technologies
• Demonstrated ability to lead complex designs through successful silicon bring-up. Strong problem-solving skills and ability to work independently on complex designs.
• Expert-level experience with Cadence Innovus and/or Synopsys ICC2 / Fusion Compiler.
• Strong proficiency in PrimeTime STA.
• Experience with RedHawk, or equivalent PI tools.
• Familiarity with Calibre DRC/LVS and sophisticated foundry signoff flows.
• Experience with FinFET and sub-10nm nodes strongly preferred.

Preferred Qualifications

• Direct experience with HBM2E / HBM3 / HBM3E products.
• Understanding of TSV-based designs and micro-bump layouts.
• Experience with die-to-die interfaces and wide parallel buses.
• Knowledge of advanced packaging (2.5D interposer, chiplets).
• Strong Tcl / Python scripting for PD flow automation.

(LLM)
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