Top Hardware Hardware Engineer Jobs in San Francisco, CA

The Senior Formal Verification Engineer will verify sophisticated ASIC builds using formal methods, collaborate with architecture teams, develop verification environments, and support silicon debug.

Seeking a Senior Physical Design Engineer with expertise in chip-level implementation, EDA tools, and low-power design to enhance AI hardware capabilities.

Seeking an experienced DFT Verification Engineer to ensure ASIC DFT logic correctness, building robust verification environments, and collaborating with design engineers on high-quality silicon delivery.

Participate in the Career Accelerator Program as a Digital IC Design Engineer, focusing on designing digital circuits, collaborating with teams, and developing product specifications.

Lead design and implementation of digital IC/ASIC/SoC for medical imaging technology, owning RTL and validation processes with collaboration across teams.

Design and implement SystemVerilog RTL for high-speed ASIC compute, memory, and networking subsystems. Define microarchitecture, optimize Power/Performance/Area, collaborate with verification/physical teams, prototype features with architects/software, mentor junior engineers, and improve design flow using AI and automation.

The Senior Mask Layout Engineer will conduct Python-driven mask layouts, manage internal libraries, perform physical verifications, and collaborate on quantum computing designs.

Responsible for evaluating and developing new compute technologies, creating solutions for customer engagements, and maintaining partnerships within the compute domain.

As an ASIC Design Verification Engineer, you will develop and execute verification strategies for AI inference ASICs, ensuring functional correctness and performance, while collaborating with design and architecture teams.

The Sr. Hardware Design Engineer leads ASIC and FPGA projects, defining architecture, guiding RTL development, and mentoring junior engineers to deliver high-quality silicon solutions.