Jobs at d-Matrix

The Principal Architect will analyze ML workloads, contribute to hardware/software features for inference accelerators, and develop analytical performance models.

Contract SRE to build, operate, and automate colo, on‑prem GPU clusters, and cloud infrastructure. Own provisioning, IaC (Terraform/Ansible), observability (Prometheus/Grafana or DataDog), incident response, runbooks, and customer-facing platform reliability.

First dedicated PR hire to build and lead d-Matrix's public relations: own media relations, pitch reporters, write press releases, manage external agency, support executive communications, develop analyst and influencer relationships, and run awards and media impact tracking.

Own and scale indirect procurement covering IP/software licensing, consulting/professional services, engineering lab/hardware equipment, and corporate/facilities services. Lead sourcing, RFQ/RFPs, contract negotiations (MSA/SOW, IP licenses), procure-to-pay via Zip/NetSuite, vendor management, cost reduction, compliance, and cross-functional alignment with Engineering, Legal, Finance, HR, and Operations.

Build and lead the SRE function from scratch: hire and manage a 3–5 person team, define SLOs/SRIs and incident processes, own reliability across colo/on-prem/cloud, implement observability and IaC (Terraform/Ansible), drive shared storage migration and FinOps, serve as senior escalation for incidents, and partner with DevOps and engineering on HPC workload requirements.

Lead junior team members in test planning, automation, and execution of software for AI compute engine, developing test suites and infrastructures, and collaborating on test coverage and results.

Lead the hardware development for AI accelerator platforms, focusing on high-performance designs, cross-functional collaboration, and mentorship of junior engineers.

Responsible for end-to-end manufacturing readiness and execution for new and sustaining hardware products, managing cross-functional teams and NPI phases while ensuring quality and cost adherence.

Responsible for developing, enhancing, and maintaining software kernels for AI hardware, mapping algorithms to architectures, and building software deliverables.

Lead end-to-end program management for post-silicon and system hardware development, coordinating firmware, board bring-up, validation, qualification, and NPI across global teams. Define milestones, metrics, dashboards, and playbooks; manage risks, external partners, and dependencies; and provide leadership updates to ensure predictable delivery and scalable processes.

Lead the layout design for high-complexity AI accelerator cards, manage constraints across designs, and drive automation for PCB layouts ensuring the highest signal integrity and efficient power delivery.

As a Senior Staff Software Engineer, you will develop and maintain AI deployment software, optimizing hardware-software co-design, and work closely with various experts to enhance infrastructure.

The Design Verification Engineer will lead SoC verification cycles, utilizing methodologies like UVM/OVM, and contributing to innovative AI architectures.

The Principal Technical Program Manager will lead engineering excellence, implement agile practices, and manage software program delivery at scale while liaising between software teams and leadership.

Design analog-mixed signal integrated circuits, optimize for low power performance, and collaborate on silicon bring up and debugging.

The Principal Technical Program Manager will drive engineering excellence in chip development, ensuring predictable project delivery and fostering collaboration between teams.

Develop, enhance, and maintain software kernels for AI hardware. Collaborate with teams to optimize hardware-software co-design and build compiler infrastructure.

Lead full life-cycle technical recruiting for hardware and software roles, source deep-tech talent, manage candidates through the interview process, build ATS reporting and dashboards, partner strategically with hiring managers, and drive adoption of AI-powered sourcing and screening tools.

Responsible for architecture, development, and validation of firmware/software for AI inference on multiprocessor SoCs, ensuring runtime performance. Collaborate with hardware teams and deliver quality code.

Lead end-to-end LLM inference engineering: prototype and deploy optimized inference systems across heterogeneous hardware. Build POCs, implement custom kernels and operator optimizations, drive quantization, sparsity, and batching strategies, maintain runtimes and serving frameworks, and contribute to distributed inference and performance profiling while collaborating with hardware, product, and business teams.