Jobs at d-Matrix

Build and lead the Site Reliability Engineering function across cloud, colocation, on-premises labs, and customer-facing services. Establish SLOs, observability, incident management, IaC automation, self-healing infrastructure, FinOps, capacity planning, and shared-storage architecture. Lead SRE and data center teams, hire and develop engineers, manage reliability and technical direction, and serve as the senior incident escalation point.

Leads rack-scale mechanical design for AI inference hardware, covering chassis, sheet metal enclosures, cooling architectures, and high-power connections. Owns systems from concept through validation, NPI, and mass production. Responsibilities include reliability testing, CAD and FEA, tolerance analysis, supplier and ODM management, production debugging, root-cause analysis, liquid-cooled rack integration, and mentoring engineers. Requires strong OCP, data center hardware, manufacturability, and mechanical leadership experience.

Own compensation analytics, market benchmarking, salary structures, job leveling, internal equity, merit and bonus modeling, and HR reporting. Manage core People Operations processes including onboarding, offboarding, records, payroll coordination, benefits, and HR systems administration. Partner with HR, business, recruiting, mobility, legal, and employee relations teams to support data-driven HR services and maintain compliant policies and procedures.

Owns the HR technology ecosystem, people data governance, analytics, workflows, integrations, and process automation across People Operations. The role administers HRIS and related platforms, improves employee lifecycle processes, develops dashboards and controls, supports payroll and benefits data flows, and leads HR technology workstreams for mergers and acquisitions. It partners cross-functionally to implement systems, resolve data issues, and apply AI to improve HR productivity.

Leads full-cycle PCB layout for complex AI accelerator cards and system baseboards. Owns high-speed routing, constraint management, stack-up definition, power delivery layouts, and design methodology. Develops SKILL, Python, or TCL automation for layout audits and reporting, and partners with power, ASIC, fabrication, and manufacturing teams to ensure DFM, DFT, DFA, and high-yield production. Requires expertise in high-density, high-speed PCB design, including 112G/224G SerDes, DDR5/HBM, HDI, and advanced materials.

Analyze emerging AI workloads and build analytical performance models and architecture simulators for current and future AI inference accelerator hardware. Collaborate with hardware, compiler, inference server, kernel, and product teams to validate assumptions, identify HW/SW optimization opportunities, incorporate architecture research, and document methodologies. The role is a hands-on technical contributor focused on performance analysis across the hardware/software boundary.

Design analog-mixed signal integrated circuits, optimize for low power performance, and collaborate on silicon bring up and debugging.

Develop, enhance, and maintain software kernels for AI hardware. Collaborate with teams to optimize hardware-software co-design and build compiler infrastructure.

Responsible for architecture, development, and validation of firmware/software for AI inference on multiprocessor SoCs, ensuring runtime performance. Collaborate with hardware teams and deliver quality code.

Lead end-to-end LLM inference engineering: prototype and deploy optimized inference systems across heterogeneous hardware. Build POCs, implement custom kernels and operator optimizations, drive quantization, sparsity, and batching strategies, maintain runtimes and serving frameworks, and contribute to distributed inference and performance profiling while collaborating with hardware, product, and business teams.

Lead full life-cycle technical recruiting for hardware and software roles, source deep-tech talent, manage candidates through the interview process, build ATS reporting and dashboards, partner strategically with hiring managers, and drive adoption of AI-powered sourcing and screening tools.

Responsible for defining qualification strategies for AI compute platforms, ensuring hardware reliability through testing, failure analysis, and collaboration across teams.

Responsible for power estimation, architectural tool development for AI workloads, and optimizing performance monitoring in micro-architecture and RTL. Collaborate with teams for design integration and silicon validation.

As a Compiler Architect, you'll design and implement a scalable MLIR-based compiler for cloud-based AI inference, focusing on optimizing large-scale AI models and architecting efficient software pipelines for deployment.

As a Principal Software Engineer, you will develop and maintain software kernels for AI hardware, collaborating on full-stack optimization and compiler infrastructure.

Own transistor-level analog design for SerDes clocking, including PLLs, DLLs, phase interpolators, clock distribution, and CDR loops. Model loop dynamics, jitter, and phase noise; develop verification environments; drive advanced-node layout; provide behavioral models; and lead silicon bring-up and bench characterization. Collaborate with datapath, DSP, digital, and firmware teams to close timing, jitter, and calibration requirements across the SerDes macro.

Design and implement efficient algorithms to optimize LLM inference on DNN accelerators. Collaborate with mathematicians, ML researchers, and engineers to apply advanced algorithmic and numerical techniques for high-impact generative AI performance improvements.

The Principal Architect will analyze ML workloads, contribute to hardware/software features for inference accelerators, and develop analytical performance models.

Lead junior team members in test planning, automation, and execution of software for AI compute engine, developing test suites and infrastructures, and collaborating on test coverage and results.

Lead the hardware development for AI accelerator platforms, focusing on high-performance designs, cross-functional collaboration, and mentorship of junior engineers.