Jobs at d-Matrix

Design and analyze analog-mixed signal integrated circuits for AI inference accelerators, focusing on circuit design, performance analysis, simulations, and collaborating with layout and backend engineers.

Responsible for defining qualification strategies for AI compute platforms, ensuring hardware reliability through testing, failure analysis, and collaboration across teams.

Responsible for architecture, development, and validation of firmware/software for AI inference on multiprocessor SoCs, ensuring runtime performance. Collaborate with hardware teams and deliver quality code.

As a Compiler Architect, you'll design and implement a scalable MLIR-based compiler for cloud-based AI inference, focusing on optimizing large-scale AI models and architecting efficient software pipelines for deployment.

The Senior Staff Signal Integrity Engineer drives SI/PI strategy for AI accelerators, leads modeling/simulation, optimizes power delivery networks, and provides technical mentorship.

Responsible for power estimation, architectural tool development for AI workloads, and optimizing performance monitoring in micro-architecture and RTL. Collaborate with teams for design integration and silicon validation.

As a Runtime Engineer Intern at d-Matrix, you'll work on embedded systems development, Linux software, and security projects, collaborating within an inclusive team.

The Principal Architect will analyze ML workloads, contribute to hardware/software features for inference accelerators, and develop analytical performance models.

Responsible for developing, enhancing, and maintaining software infrastructure to support ML accelerator systems. Requires extensive experience in DevOps and software infrastructure development.

Design and verify FPGA solutions for AI inference management, develop secure boot and power management features, and collaborate on hardware/software integration.

The intern will assist in power delivery network analysis, perform lab measurements, support impedance analysis, and document findings alongside senior engineers.

Lead the development of AI server and cluster solutions, engaging with customers and stakeholders to deliver high-quality products. Collaborate across teams to optimize performance and validate design requirements.

The role involves designing and verifying micro-architecture for AI sub-systems, focusing on RTL development and silicon validation.

The intern will design and implement AI solutions for manufacturing workflows, focusing on LLMs to improve operational efficiency, data management, and collaboration across teams.

Responsible for developing, enhancing, and maintaining software kernels for AI hardware, mapping algorithms to architectures, and building software deliverables.

Lead junior team members in test planning, automation, and execution of software for AI compute engine, developing test suites and infrastructures, and collaborating on test coverage and results.

Intern will engage in functional hardware verification, utilize UVM methodologies, and employ formal verification techniques to enhance simulation and productivity in AI technologies.

Lead the hardware development for AI accelerator platforms, focusing on high-performance designs, cross-functional collaboration, and mentorship of junior engineers.

The Principal System Power Engineer leads the architecture of power systems for AI accelerators, focusing on efficiency, power integrity, and collaboration across engineering teams to deliver high-performance solutions.

Lead the layout design for high-complexity AI accelerator cards, manage constraints across designs, and drive automation for PCB layouts ensuring the highest signal integrity and efficient power delivery.