TetraMem Logo

TetraMem

Analog Layout Engineer

Reposted 2 Months Ago
Be an Early Applicant
In-Office
San Jose, CA, USA
110K-300K Annually
Senior level
In-Office
San Jose, CA, USA
110K-300K Annually
Senior level
The Analog Layout Engineer will design and implement analog and mixed-signal layouts, lead layout engineers, and ensure design quality meets guidelines.
The summary above was generated by AI

Job Summary:
We are seeking an experienced Analog Layout Engineer to join our team. The Analog Layout Engineer will be responsible for designing and implementing analog and mixed-signal layout designs for integrated circuits. This role requires a strong understanding of analog design principles and the ability to work closely with the design team to meet project goals.

Responsibilities:

  • Lead a team of layout engineers to produce complex analog and mixed-signal blocks with high-quality layout
  • Collaborate with project managers and design engineers to understand project requirements
  • Drive critical floor-planning decisions and key layout methodology
  • Ensure that all designs meet project requirements and adhere to design guidelines
  • Review and approve final layout designs for production
  • Stay up-to-date with industry trends and advancements in design software and techniques
  • Attend project meetings, presentations, and other events as needed

Requirements:

  • B.S. EE and 8+ years of relevant industry experience or equivalent
  • Experience in analog and mixed-signal layout design of deep submicron CMOS circuits and recent experience on advance nodes
  • Proficiency in industry-standard design software, such as Cadence Virtuoso, Calibre DRC, LVS
  • Strong understanding of layout design principles and best practices
  • Excellent communication, collaboration, and leadership skills
  • Ability to manage multiple projects simultaneously while maintaining attention to detail
  • Demonstrated ability to work independently and as part of a team
  • Strong problem-solving and decision-making skills

Salary Range: $110,000 - $300,000 / year

TetraMem celebrates diversity and is committed to creating an inclusive environment for all employees. We are proud to be an Equal Opportunity Employer and welcome applicants from all backgrounds. Qualified candidates will receive consideration for employment without regard to race, color, religion, creed, sex, gender identity or expression, sexual orientation, national origin, ancestry, age, marital status, medical condition, disability, genetic information, military or veteran status, or any other characteristic protected by applicable federal, state, or local law.

TetraMem is committed to providing reasonable accommodations to qualified applicants with disabilities throughout the recruitment process. Applicants requiring accommodation may contact Human Resources for assistance.

To ensure a fair, consistent, and efficient hiring process, all candidates must apply through TetraMem’s official ClearCompany Applicant Tracking System (ATS). Applications submitted through the ATS allow our hiring team to evaluate candidates using a standardized process and ensure timely communication throughout the recruitment process. To promote equal consideration for all applicants, applications submitted outside of the ClearCompany ATS, including direct emails, LinkedIn messages, or unsolicited submissions to employees, may not be reviewed or considered.

We encourage all interested candidates to apply through the official TetraMem Careers page.

HQ

TetraMem Newark, California, USA Office

Newark, CA, United States

Similar Jobs

24 Days Ago
In-Office
149K-282K Annually
Senior level
149K-282K Annually
Senior level
Cloud • Information Technology • Internet of Things • Professional Services • Software
Owns analog and mixed-signal ASIC layout from floorplanning through physical verification, sign-off, tapeout, and post-silicon bring-up. The role focuses on high-speed optical interconnects, parasitic and thermal optimization, signal integrity, block-to-top integration, and advanced FINFET processes. Responsibilities include using custom layout and EDA tools, supporting tapeout flows, collaborating with circuit, packaging, and CAD teams, developing methodologies, and mentoring engineers.
Top Skills: AsicCadence VirtuosoCalibreDrcEm/Ir AnalysisErcFinfetLinuxLvsParasitic ExtractionPerlPythonSocTcl
29 Days Ago
In-Office
Santa Clara, CA, USA
Entry level
Entry level
HR Tech • Information Technology
The job description provides no details beyond the title. The role appears focused on analog integrated-circuit layout engineering.
Top Skills: Analog Ic Layout
One Month Ago
In-Office
145K-175K Annually
Senior level
145K-175K Annually
Senior level
Semiconductor • Manufacturing
Own physical layout and verification of complex analog and mixed-signal ICs at block and full-chip levels. Develop floorplans, optimize placement, perform LVS and DRC verification, resolve manufacturability issues, and collaborate with analog, digital, packaging, and cross-functional teams through tapeout. The role requires expertise in analog CMOS circuits, device physics, EDA tools, high-voltage BCD and mixed-voltage designs, with preferred experience in high-speed, precision, data converter, and BiCMOS layouts.
Top Skills: BcdBicmosCadenceCalibreCmosDrcLdmosLvsMentor GraphicsSkillStiTanner

What you need to know about the San Francisco Tech Scene

San Francisco and the surrounding Bay Area attracts more startup funding than any other region in the world. Home to Stanford University and UC Berkeley, leading VC firms and several of the world’s most valuable companies, the Bay Area is the place to go for anyone looking to make it big in the tech industry. That said, San Francisco has a lot to offer beyond technology thanks to a thriving art and music scene, excellent food and a short drive to several of the country’s most beautiful recreational areas.

Key Facts About San Francisco Tech

  • Number of Tech Workers: 365,500; 13.9% of overall workforce (2024 CompTIA survey)
  • Major Tech Employers: Google, Apple, Salesforce, Meta
  • Key Industries: Artificial intelligence, cloud computing, fintech, consumer technology, software
  • Funding Landscape: $50.5 billion in venture capital funding in 2024 (Pitchbook)
  • Notable Investors: Sequoia Capital, Andreessen Horowitz, Bessemer Venture Partners, Greylock Partners, Khosla Ventures, Kleiner Perkins
  • Research Centers and Universities: Stanford University; University of California, Berkeley; University of San Francisco; Santa Clara University; Ames Research Center; Center for AI Safety; California Institute for Regenerative Medicine

Sign up now Access later

Create Free Account

Please log in or sign up to report this job.

Create Free Account