Lead ASIC/SoC RTL design, simulation, and verification at TetraMem. Collaborate with cross-functional teams, guide junior engineers, and optimize designs for performance and efficiency.

The role involves defining and implementing test plans for SoC verification, developing testbench and test cases, maintaining verification infrastructure, debugging simulation failures, and mentoring team members.

The role involves designing memory IC projects, optimizing circuits, developing test plans, and collaborating with engineering teams to resolve design issues and ensure successful tape-out.

Responsible for the verification of analog and mixed-signal ICs using verification methodologies and tools. Develops testbenches and collaborates with design teams to ensure functionality and reliability.