Digital - Staff Digital Design Engineer - PHY

Key Responsibilities:

• Architecture & RTL Design
• Own D2D PHY digital design from microarchitecture definition through synthesis and PD handoff
• Design data path and clocking architecture for UCIe-compliant advanced package PHY
• Write RTL for link training, calibration engines, rate adaptation, CDC, FIFO alignment, and lane deskew
• Create microarchitecture specs with power analysis, latency metrics, and performance characterization
• Make architectural trade-offs balancing performance, power, area, and timing 
• Synthesis & Optimization
• Drive synthesis optimization: area, timing, power, QoR
• Create comprehensive SDC constraints for multi-clock domains, false paths, multi-cycle paths, CDC
• Generate UPF power specifications with voltage domains, isolation, and retention
• Establish LINT/CDC flows with rulesets and waiver management
• Deliver synthesis-ready netlists with handoff documentation for physical design
• Technical Leadership & Collaboration
• Coordinate with analog PHY team on digital control for TX/RX, PLL, calibration
• Partner with verification team on testbench requirements, coverage goals, and protocol compliance
• Collaborate with physical design on placement guidelines, clock tree requirements, routing constraints
• Work with firmware team on register interfaces, link training sequences, runtime control
• Mentor 2-3 digital designers on frontend design and synthesis optimization
• Drive design reviews and technical decisions across teams

Required Qualifications:

• 8+ years digital frontend design with 4+ years in PHY or high-speed interfaces
• 3+ successful tapeouts as design lead in advanced nodes (7nm or below)
• Deep expertise in D2D PHY, DDR PHY, or SerDes digital design
• Expert SystemVerilog RTL design with strong synthesis optimization skills
• Strong understanding of UCIe or other high-speed interfaces like DDR/Serdes
• Advanced CDC design, link training protocols, elastic buffer architectures
• Hands-on with synthesis tools (Synopsys DC/Fusion Compiler or Cadence Genus)
• Experience with SDC constraints, UPF, STA methodology
• Proven ability to lead frontend design and coordinate across teams 

Preferred Qualifications:

• 12+ years with demonstrated technical leadership
• UCIe PHY design or certification experience
• DDR4/DDR5/LPDDR PHY or DFI interface experience
• SerDes digital control (TX/RX equalization, CDR), PCIe PHY, or CXL PHY experience
• Advanced packaging knowledge: 2.5D, 3D, organic substrate
• Firmware development for PHY control or low-level driver implementation
• Python/Perl/Tcl scripting for design automation
• Publications or patents in PHY design