Director, Physical Design & CAD Methodology (ASIC/SoC)

Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received.

Meet the Team

The Common Hardware Group (CHG) creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms—like Silicon One—are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and work quickly. Join us to power the future of the digital world.

Your Impact

• Define the global physical design methodology strategy across all phases: synthesis, floor planning, placement, clock tree synthesis (CTS), routing, timing closure, and physical verification.
• Architect and deploy advanced CAD flows to support complex, high-performance System-on-Chip (SoC) and Application-Specific Integrated Circuit (ASIC) designs.
• Drive innovation in hierarchical design, multi-die/chiplet integration, and 2.5D/3D IC Design methodologies.
• Manage, mentor, and grow a high-performing team of CAD and physical design methodology engineers.
• Allocate engineering resources efficiently to support concurrent, multi-project execution timelines.
• Develop a culture of continuous learning, automation, and technical excellence.
• Serve as the primary technical liaison with major EDA vendors (e.g., Synopsys, Cadence, Siemens).
• Evaluate, benchmark, and select state-of-the-art EDA tools to improve engineering productivity and design quality.
• Negotiate tool licensing requirements, influence vendor product roadmaps, and manage the CAD budget.
• Drive the creation of robust scripting infrastructure (using Tcl, Python, Perl) to automate repetitive tasks and ensure flow consistency.
• Explore and integrate AI/ML-driven EDA features to optimize PPA and shorten turnaround times.
• Partner closely with RTL Design, DFT (Design for Test), Architecture, and Physical Implementation teams to ensure seamless handoffs and tool interoperability.
• Collaborate with external foundries to integrate Process Design Kits (PDKs) and resolve complex deep sub-micron physical effects (e.g., electromigration, IR drop, thermal management).

Minimum Qualifications

• Master’s or Ph.D. degree in Electrical Engineering, Computer Engineering, or a highly related technical field with 10+ years of experience in ASIC/SoC physical design and CAD methodology.
• 5+ years of experience in a formal leadership or people management role
• Experience navigating the complexities of advanced process geometries (7nm, 5nm, 3nm and 2nm)
• Experience with full RTL-to-GDSII design flows
• Experience with physical verification (DRC, LVS, ERC), Static Timing Analysis (STA), sign-off processes, and power integrity (IR drop and electromigration)

Preferred Qualifications

• Proficiency in EDA tool suites (e.g., Innovus, Fusion Compiler, PrimeTime, Calibre

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. 

We are Cisco, and our power starts with you. 

Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process.

U.S. employees are offered benefits, subject to Cisco’s plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance. Please see the Cisco careers site to discover more benefits and perks.  Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time.

U.S. employees are eligible for paid time away as described below, subject to Cisco’s policies:

• 10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees

• 1 paid day off for employee’s birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco

• Non-exempt employees** receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees

• Exempt employees participate in Cisco’s flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations)

• 80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next

• Additional paid time away may be requested to deal with critical or emergency issues for family members

• Optional 10 paid days per full calendar year to volunteer

For non-sales roles, employees are also eligible to earn annual bonuses subject to Cisco’s policies.

Employees on sales plans earn performance-based incentive pay on top of their base salary, which is split between quota and non-quota components, subject to the applicable Cisco plan. For quota-based incentive pay, Cisco typically pays as follows:

• .75% of incentive target for each 1% of revenue attainment up to 50% of quota;

• 1.5% of incentive target for each 1% of attainment between 50% and 75%;

• 1% of incentive target for each 1% of attainment between 75% and 100%; and

• Once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation.

For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay 0% up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid.

The applicable full salary ranges for this position, by specific state, are listed below:

New York City Metro Area:

Non-Metro New York state & Washington state:

* For quota-based sales roles on Cisco’s sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined.

** Employees in Illinois, whether exempt or non-exempt, will participate in a unique time off program to meet local requirements.