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Intel

Principal Technical Program Manager - DTCO & Design Technology Integration

Posted 4 Days Ago
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In-Office
Santa Clara, CA, USA
220K-311K Annually
Expert/Leader
In-Office
Santa Clara, CA, USA
220K-311K Annually
Expert/Leader
Leads large-scale technical programs spanning design-technology co-optimization, circuit design, foundational IP, and design enablement. Partners with engineering teams, customers, EDA vendors, and ecosystem stakeholders to align technical strategy, drive execution, improve organizational processes, and represent program roadmaps to senior leadership. Responsibilities also include mentoring engineers, workforce development, hiring, training, budget planning, and organizational transformation.
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Job Details:

Job Description: 

The Advanced Design and Foundational IP (AD-FIP) organization within Intel's Design Technology Platform (DTP) is seeking a dynamic and technically accomplished DTCO & Design Technology Integration Technical Program Manager to help lead and shape one of Intel Foundry's most strategically critical organizations. AD-FIP is chartered with technology definition, design-technology co-optimization (DTCO), and the development of test chip IP, reference IP, and foundational IP across all Intel Foundry nodes.


Responsibilities:

  • Serve as a key leadership partner and force multiplier for the AD-FIP organization, driving technical projects, enabling organizational transformation, and ensuring operational excellence across a broad and highly technical portfolio.
  • Engage across DTP and with cross-functional stakeholders to align technical vision with organizational strategy, accelerate execution, and cultivate a high-performing, innovative team culture.
  • Lead and influence technical initiatives spanning circuit design, DTCO, and foundational IP development, while simultaneously driving critical organizational processes including hiring, workforce development, training programs, and budget planning.
  • Partner directly with DTP staff members to drive targeted lead customer engagements, helping to shape messaging, ensure technical alignment, and represent AD-FIP's capabilities and roadmap with Intel Foundry's most strategic customers.
  • Lead and coordinate a diverse set of external engagements with EDA vendors and ecosystem partners on DTCO and technology definition, ensuring that Intel Foundry's foundational IP and design enablement strategy is well-represented, differentiated, and co-developed with the broader industry ecosystem.
  • Mentor engineers across the organization, act as a change agent to drive continuous improvement, and help define the technical and cultural direction of AD-FIP.
  • Represent the organization in key forums, synthesize complex technical and operational information for senior leadership, and ensure that AD-FIP's programs are executed with rigor, clarity, and impact.

 

Required Skills and Experience

  • Bring a rare combination of deep technical credibility in circuit and/or system design, strong cross-functional communication skills, and the organizational acumen to operate effectively at the intersection of technology and leadership.
  • Demonstrated expertise in managing large-scale engineering projects, programs, or teams with a focus on hardware, software, technology platforms, or manufacturing.
  • Proficiency in engineering project management tools and methodologies to drive strategic objectives.
  • Proven ability to analyze technical challenges and deliver innovative solutions within engineering domains.
  • Advanced leadership skills with proven experience in coaching and mentoring engineering teams to achieve high performance.
  • Strong communication and collaboration skills to work effectively across diverse teams and stakeholders.
  • Ability to innovate processes and procedures to improve organizational effectiveness and project outcomes.
  • Strategic mindset with experience in influencing executive decisions and driving program-level milestones in alignment with business priorities.

Qualifications:
  • Degree in engineering or related field
  • Bachelor's degree with 12+ years of relevant experience, Masters degree with 8+ years of experience or PhD with 6+ years of experience.

Explore this exciting opportunity to lead transformative engineering programs and drive innovation at Intel. Become a key contributor to groundbreaking advancements while fostering growth and excellence within your team.

          

Job Type:Experienced Hire

Shift:Shift 1 (United States of America)

Primary Location: US, Oregon, Hillsboro

Additional Locations:US, California, Santa Clara, US, Texas, Austin

Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustThis role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.



Annual Salary Range for jobs which could be performed in the US: $220,320.00-311,040.00 USD

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

*

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
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