Marvell Technology Logo

Marvell Technology

Principal ATE Test Development Engineer

Reposted Yesterday
Be an Early Applicant
In-Office
Santa Clara, CA, USA
137K-205K Annually
Expert/Leader
In-Office
Santa Clara, CA, USA
137K-205K Annually
Expert/Leader
Lead development of ATE test solutions for characterization, production, and wafer sort on Advantest 93K/Teradyne. Design high-speed ATE hardware, create test plans, convert design test patterns to ATE format, optimize test flows, collaborate with DFx/design, and ensure DFT/MBIST and high-speed interface compliance.
The summary above was generated by AI

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. 

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. 

Your Team, Your Impact

As a test development principal engineer in the Operations business group, you will test features on the silicon semiconductor chips Marvell produces for internal and external customers. You will make sure we don’t ship out any underperforming units. You’ll work closely with design to make sure their chip features are testable and that the results meet the customer’s specifications. You may even have to write new code or develop new testing strategies when our chips outpace the capabilities of current testing equipment.

What You Can Expect

Lead Cutting-Edge ATE Test Solutions: As a Senior Level Test Engineer, you will spearhead the development of ATE test solutions for characterization, production, and wafer sort on Advantest 93K and/or Teradyne tester platforms. Your work will be at the forefront of technology, ensuring our products meet the highest standards. 

  • Innovate High-Speed Testing Hardware: Design and develop advanced ATE test hardware for high-speed testing, pushing the boundaries of what's possible and ensuring our products are ready for the future. 

  • Craft Comprehensive Test Plans: Create detailed test plans and methodologies documentation that meet stringent product specifications, ensuring every product we release is of the highest quality. 

  • Collaborate with Cross-Functional Teams: Participate in testability and test plan reviews with DFx and Design teams, working together to define and enhance yield and test methodologies. Your input will be crucial in driving innovation and efficiency. 

  • Transform Test Patterns: Convert test patterns from the design simulation environment to ATE format, bridging the gap between design and production. 

  • Optimize and Innovate: Play a lead role in optimizing test flows, reducing test times, removing unnecessary steps, improving yields, and releasing production test programs in collaboration with product engineers. Your contributions will directly impact the efficiency and success of our products. 

  • Opportunities for Growth: At Marvell, we believe in nurturing talent and providing opportunities for professional development. As you excel in your role, you will have the chance to take on more responsibilities, lead larger projects, and advance your career within the company. We are committed to supporting your growth and helping you achieve your career goals. 

 

What We're Looking For

  • Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 10+ years of related professional experience. Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 5+ years of experience.
  • Expertise in test program development on the Advantest 93K and/or Teradyne tester platform(s). 
  • Demonstrable experience in ATE testing (critical skill), test methodology, silicon process, DFT/DFM, and high-speed digital testing. 
  • Strong knowledge of C/C++, Perl, Python, and Linux environment. 
  • Testing of high-speed interfaces (NRZ/PAM4)
  • Solid understanding of scan and MBIST DFT test methodologies.
  • Design of complex and high-performance ATE hardware.
  • Effective interpersonal, teamwork, communication, and problem-solving skills. 
  • Highly motivated individual contributor with the ability to multi-task in a fast-paced environment. 
  • Marvell also provides additional cash bonuses and performance-based compensation. 

Expected Base Pay Range (USD)

136,880 - 205,000, $ per annum

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

This role is eligible to participate in Marvell's bonus and equity plans, including a new hire equity grant and annual equity refreshers, ensuring you are rewarded for your contributions and remain invested in the company's long-term success.

Additional Compensation and Benefit Elements 

Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at [email protected].

Interview Integrity 

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

#LI-TT1
HQ

Marvell Technology Santa Clara, California, USA Office

5488 Marvell Ln, Santa Clara, CA, United States, 95054

Similar Jobs

One Month Ago
In-Office
Santa Clara, CA, USA
137K-205K Annually
Senior level
137K-205K Annually
Senior level
Artificial Intelligence • Automotive • Semiconductor
Develops semiconductor test programs on the Advantest 93K platform for characterization, production, and wafer sort. Designs tester hardware, converts test patterns, creates test plans, improves yield and test time, and supports testability reviews with design, DFT, and DFM teams. The role requires expertise in ATE testing, silicon processes, high-speed digital testing, and programming in C/C++, Perl, and Python within Linux.
Top Skills: Advantest 93K AteCC++Design For Manufacturability (Dfm)Design For Test (Dft)High-Speed Digital TestingLinuxPerlPython
One Month Ago
In-Office
Santa Clara, CA, USA
137K-205K Annually
Senior level
137K-205K Annually
Senior level
Artificial Intelligence • Automotive • Semiconductor
Develops semiconductor test programs on the Advantest 93K platform for characterization, production, and wafer sort. Designs tester hardware for high-speed testing, creates test plans, converts simulation patterns to ATE formats, and leads test-flow optimization, yield improvement, and production releases. Collaborates with design, DFT/DFM, and product engineering teams to ensure chip testability and compliance with customer specifications. Requires extensive ATE experience, programming skills, and semiconductor test expertise.
Top Skills: Advantest 93K AteC/C++DfmDftHigh-Speed Digital TestingLinuxPerlPythonSemiconductor Testing
2 Months Ago
In-Office
Santa Clara, CA, USA
137K-205K Annually
Expert/Leader
137K-205K Annually
Expert/Leader
Artificial Intelligence • Automotive • Semiconductor
Lead development of ATE test solutions for characterization, wafer sort, and production on Advantest 93K/Teradyne UltraFLEX. Design high-speed test hardware, define test methodologies, translate simulation patterns to ATE programs, optimize test flows, and collaborate cross-functionally to improve yield and release production test programs.
Top Skills: Advantest 93KAteCC++DfmDftJavaLinuxPerlPythonTeradyne Ultraflex

What you need to know about the San Francisco Tech Scene

San Francisco and the surrounding Bay Area attracts more startup funding than any other region in the world. Home to Stanford University and UC Berkeley, leading VC firms and several of the world’s most valuable companies, the Bay Area is the place to go for anyone looking to make it big in the tech industry. That said, San Francisco has a lot to offer beyond technology thanks to a thriving art and music scene, excellent food and a short drive to several of the country’s most beautiful recreational areas.

Key Facts About San Francisco Tech

  • Number of Tech Workers: 365,500; 13.9% of overall workforce (2024 CompTIA survey)
  • Major Tech Employers: Google, Apple, Salesforce, Meta
  • Key Industries: Artificial intelligence, cloud computing, fintech, consumer technology, software
  • Funding Landscape: $50.5 billion in venture capital funding in 2024 (Pitchbook)
  • Notable Investors: Sequoia Capital, Andreessen Horowitz, Bessemer Venture Partners, Greylock Partners, Khosla Ventures, Kleiner Perkins
  • Research Centers and Universities: Stanford University; University of California, Berkeley; University of San Francisco; Santa Clara University; Ames Research Center; Center for AI Safety; California Institute for Regenerative Medicine

Sign up now Access later

Create Free Account

Please log in or sign up to report this job.

Create Free Account