Design and optimize high-speed precision CMOS analog circuits for automated test equipment products. Responsibilities include circuit simulation, layout, verification, post-layout and mixed-signal analysis, architecture optimization, IC characterization, test development, and qualification. The engineer owns circuit blocks across the full IC development lifecycle and collaborates with digital, layout, test, product, and applications engineering teams.
As a Senior Analog Design Engineer, you will contribute to the design and optimization of analog circuits used in high performance ATE products. You will work closely with cross functional teams and take ownership of circuit blocks from concept through silicon validation.
In this role, you will apply strong analog design fundamentals to solve complex technical challenges, make design tradeoffs, and drive performance, reliability, and manufacturability. You will contribute throughout the full IC development lifecycle while collaborating with experienced engineers across design, layout, test, and product engineering.
Responsibilities
- Design and simulate high speed, precision CMOS circuits for ATE applications
- Perform layout, verification, and post layout simulation, including Monte Carlo, SOAC, and corner analysis
- Perform mixed signal simulations at both the channel and chip levels
- Develop and optimize circuit architectures for power, performance, and density
- Support IC characterization, test development, and qualification
- Collaborate with cross functional teams including digital design, layout, test, product, and applications engineering
Requirements
- Bachelor’s degree in Electrical Engineering or related field
- 5+ years of professional experience in analog IC design
- Strong foundation in analog CMOS circuit design
- Experience designing and analyzing feedback loops, including stability analysis and compensation
- Solid understanding of the full IC development lifecycle, from design and verification through qualification and manufacturing
- Hands on experience with analog and mixed signal EDA tools such as Cadence, Mentor Graphics, or Tanner
- Experience performing LVS and DRC verification using Cadence or Mentor tools
The anticipated annual base salary range for this position is $125,000.00 to $145,000.00. Actual compensation will be determined based on factors such as experience, skills, qualifications, education, location, and business needs.
In addition to base salary, employees may be eligible for incentive compensation and a comprehensive benefits package. This salary range represents the Company's good-faith estimate of the compensation it reasonably expects to pay for this position at the time of posting.
Similar Jobs
Semiconductor • Manufacturing
Leads analog architecture and design for complex ATE ICs, including circuit development, schematic and layout reviews, verification, mixed-signal simulation, silicon bring-up, characterization, and debugging. Provides technical leadership across projects, mentors engineers, establishes design standards, and collaborates with engineering, product, and customer teams to guide future product direction.
Top Skills:
Analog And Mixed-Signal Eda ToolsAnalog CmosAte IcsFeedback SystemsMixed-Signal SimulationStability Analysis
Semiconductor • Manufacturing
Design and develop transistor-level analog and mixed-signal circuits for CMOS image sensors. Perform block, transistor-level, and whole-chip simulations; create and optimize sensor-array readout layouts using Cadence Virtuoso and Calibre. Collaborate with verification, process, test, and applications teams to debug, characterize, and optimize fabricated image sensors from concept through product release.
Top Skills:
Analog CircuitsCad ToolsCadence VirtuosoCalibreCmosCmos Image SensorsMixed-Signal CircuitsSemiconductor Device Physics
Semiconductor • Manufacturing
Lead full-custom analog IC physical design for CMOS image sensors, including column ADC layout, floorplanning, power and clock planning, chip-level routing, parasitic analysis, physical verification, and GDS tape-out. Optimize image sensor performance, area, noise, matching, and power integrity. Develop layout methodologies, automation scripts, design rules, and SVRF files while coordinating top-level implementation resources and schedules.
Top Skills:
Analog Ic LayoutAntAsicCadence VirtuosoCalibreCmosDesign CompilerDfmDrcEdaErcGdsIc CompilerInnovusLakerLvsP2PPerlPrimetimePvsRcxSkillSkipperSpectreSvrfSynopsys HspiceTcl
What you need to know about the San Francisco Tech Scene
San Francisco and the surrounding Bay Area attracts more startup funding than any other region in the world. Home to Stanford University and UC Berkeley, leading VC firms and several of the world’s most valuable companies, the Bay Area is the place to go for anyone looking to make it big in the tech industry. That said, San Francisco has a lot to offer beyond technology thanks to a thriving art and music scene, excellent food and a short drive to several of the country’s most beautiful recreational areas.
Key Facts About San Francisco Tech
- Number of Tech Workers: 365,500; 13.9% of overall workforce (2024 CompTIA survey)
- Major Tech Employers: Google, Apple, Salesforce, Meta
- Key Industries: Artificial intelligence, cloud computing, fintech, consumer technology, software
- Funding Landscape: $50.5 billion in venture capital funding in 2024 (Pitchbook)
- Notable Investors: Sequoia Capital, Andreessen Horowitz, Bessemer Venture Partners, Greylock Partners, Khosla Ventures, Kleiner Perkins
- Research Centers and Universities: Stanford University; University of California, Berkeley; University of San Francisco; Santa Clara University; Ames Research Center; Center for AI Safety; California Institute for Regenerative Medicine
