Persimmons, Inc. Logo

Persimmons, Inc.

Senior ASIC Design Engineer

Posted 3 Days Ago
Be an Early Applicant
In-Office
San Jose, CA
Senior level
In-Office
San Jose, CA
Senior level
As a Senior ASIC Design Engineer, you will design high performance compute and data transport logic for AI models, collaborate on integration, develop verification strategies, and improve productivity through automation.
The summary above was generated by AI

Who we are: 

Persimmons is building the infrastructure that will power the next decade of AI. Founded in 2023 by veteran technologists from the worlds of semiconductors, AI systems, and software innovation, We’re on a mission to enable smarter devices, more sustainable data centers, and entirely new applications the world hasn’t imagined yet.

Why join us:

We’re growing fast and looking for bold thinkers, builders, and curious problem-solvers who want to push the limits of AI hardware and software. If you're ready to join a world-class team and play a critical role in making a global impact - we want to talk to you.

What you’ll do:

As a Persimmons Senior ASIC Design Engineer, you will be responsible for building and verifying the Persimmons Chiplet that will run the smallest to largest AI models. Your primary duties and responsibilities include:

  • Design High Performance Compute & High Speed Data Transport logic optimized for AI inference workloads.
  • Collaborate to integrate 3rd party & open source IP.
  • Partner with DV engineers to develop comprehensive verification strategies, drive coverage closure, and debug complex cross-functional issues.
  • Develop automation and methodologies to improve productivity and quality.
  • Create detailed technical documentation including microarchitecture specifications, integration guides, and design reviews.
  • Contribute to architectural decisions that balance performance, power, area & schedule.
  • Collaborate with Physical Design teams to ensure RTL quality supports timing closure, power targets, and manufacturability on advanced process nodes.

Requirements

What You Bring To The Table:

  • BS/MS in Electrical Engineering, Computer Engineering, or related field
  • 5+ years of hands-on ASIC design experience with complex digital logic in SystemVerilog
  • Proven record of designing high performance compute & high speed data transport logic.
  • Experience integrating fabric & high-speed IO like PCIe/HBM/etc
  • Proficiency with testbench creation, simulation environments and synthesis flows
  • Experience with scripting languages such as Python, Perl, or TCL for automation
  • Self-motivated & able to thrive in fast-paced, ambiguous start-up environments
  • Ability to learn about AI inference & passionate about building next-generation AI silicon

Benefits
  • Competitive salary and benefits package
  • Flexible PTO
  • 401k

Please note: Our organization does not accept unsolicited candidate submissions from external recruiters or agencies. Any such submissions, regardless of form (including but not limited to email, direct messaging, or social media), shall be deemed voluntary and shall not create any express or implied obligation on the part of the organization to pay any fees, commissions, or other compensation. Direct contact of employees, officers, or board members regarding employment opportunities is strictly prohibited and will not receive a response.

Top Skills

Hbm
Pcie
Perl
Python
Systemverilog
Tcl
HQ

Persimmons, Inc. San Jose, California, USA Office

San Jose, California, United States, 95054

Similar Jobs

3 Hours Ago
In-Office
Los Angeles, CA, USA
152K-213K Annually
Senior level
152K-213K Annually
Senior level
Aerospace
Design and develop ASICs and FPGAs, implement designs using HDL, develop verification methodologies and collaborate with cross-functional teams.
Top Skills: AsicFpgaLinuxPerlPythonSystemverilogTclVerilogVhdl
3 Days Ago
In-Office
San Jose, CA, USA
Senior level
Senior level
Artificial Intelligence • Information Technology • Software • Database • Generative AI
The Senior ASIC Design Verification Engineer leads verification planning and execution for AI chip designs, collaborates with cross-functional teams, and innovates verification methodologies.
Top Skills: CC++SystemverilogUvmVerilog
4 Days Ago
In-Office
Santa Clara, CA, USA
235K-260K Annually
Senior level
235K-260K Annually
Senior level
Cybersecurity
As a Design Verification Engineer, you will verify ASICs for firewall products, define methodologies, create test plans, and debug while collaborating across teams.
Top Skills: CC++PerlPythonSystemverilogUnix ShellUvm

What you need to know about the San Francisco Tech Scene

San Francisco and the surrounding Bay Area attracts more startup funding than any other region in the world. Home to Stanford University and UC Berkeley, leading VC firms and several of the world’s most valuable companies, the Bay Area is the place to go for anyone looking to make it big in the tech industry. That said, San Francisco has a lot to offer beyond technology thanks to a thriving art and music scene, excellent food and a short drive to several of the country’s most beautiful recreational areas.

Key Facts About San Francisco Tech

  • Number of Tech Workers: 365,500; 13.9% of overall workforce (2024 CompTIA survey)
  • Major Tech Employers: Google, Apple, Salesforce, Meta
  • Key Industries: Artificial intelligence, cloud computing, fintech, consumer technology, software
  • Funding Landscape: $50.5 billion in venture capital funding in 2024 (Pitchbook)
  • Notable Investors: Sequoia Capital, Andreessen Horowitz, Bessemer Venture Partners, Greylock Partners, Khosla Ventures, Kleiner Perkins
  • Research Centers and Universities: Stanford University; University of California, Berkeley; University of San Francisco; Santa Clara University; Ames Research Center; Center for AI Safety; California Institute for Regenerative Medicine

Sign up now Access later

Create Free Account

Please log in or sign up to report this job.

Create Free Account