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Microsoft

Senior Principal Design Verification Engineer

Posted 3 Days Ago
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In-Office
Mountain View, CA, USA
166K-331K Annually
Senior level
In-Office
Mountain View, CA, USA
166K-331K Annually
Senior level
Architect and lead pre-silicon and post-silicon verification for Microsoft AI accelerator SoCs. Develop verification environments, test plans, reference models, scoreboards, assertions, coverage, constraints, and scalable scripts. Drive security verification covering secure boot, root of trust, isolation, privilege, debug, recovery, and confidential computing. Collaborate with architecture, RTL, firmware, platform, security, and product teams to debug failures and achieve silicon signoff.
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Overview

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for engineers to help achieve that mission.

The AI Silicon Engineering (AISiE) SoC Design Verification team verifies Microsoft’s latest AI accelerators, working hand in hand with systems, firmware, architecture, design, validation, and product engineering teams. We are seeking passionate, driven, and intellectually curious silicon verification engineers who can partner across these disciplines to develop the verification environments and test cases that bring these accelerators to production with high quality.

As a Senior Principal Design Verification Engineer on the AISiE SoC Design Verification team, you will architect and drive complex pre-silicon verification, including SoC security verification, for Microsoft’s AI accelerators from block to chip and system level through post-silicon validation.

#SCHIE #AISIE


Responsibilities
  • Create complex verification environments and tests, driving pre-silicon functional verification at the block, chip, and system level, reference modeling, and post-silicon validation.
  • Interact with architects and design engineers to create verification plans covering strategy, test environments and tests, and verification requirements for IP, subsystem, and SoC level verification, then create and drive test plans and test development to provide complete feature coverage.
  • Defining SoC security architecture and threat models, including secure boot, root of trust, identity, isolation, privilege, debug, lifecycle, and recovery.
  • Develop verification components such as scoreboards, sequences, constraints, assertions, and functional coverage, along with Makefiles and scripts for scalable and efficient verification.
  • Develop and implement technical solutions to complex quality and design challenges, and triage and debug testbench, simulation, and emulation failures.
  • Apply Agile development methodologies, including code reviews, sprint planning, and frequent deployment, and collaborate with teams across sites and geographies.

Qualifications

Requirememts: 

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 7+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 10+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 12+ years technical engineering experience OR equivalent experience.

Other Requirements:
Ability to meet Microsoft, customer, and/or government security screening requirements is required for this role. These requirements include, but are not limited to, the following specialized security screening:

  • Microsoft Cloud Background Check. This position is required to pass the Microsoft Cloud Background Check upon hire or transfer and every two years thereafter.
  • This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations.  As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their U.S. permanent residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.

Preferred Qualifications:

  • CPU, graphics, or NPU security architecture or micro-architecture experience.
  • Architecting confidential computing solutions for workload isolation, memory protection and encryption, trusted execution, attestation, and data-in-use protection.
  • Own hardware security microarchitecture, including key management, cryptography, secure storage, anti-rollback, access control, and hardware trust boundaries.
  • Drive end-to-end SoC security across compute, memory, I/O, chip-to-chip interfaces, firmware, and accelerators.
  • Apply verification principles, testbench architectures, and scalable stimulus generation to enable comprehensive security verification.
  • Partner across RTL, firmware, DV, PD, platform, and security teams on threat analysis, security verification, vulnerability closure, and silicon signoff.

Silicon Engineering IC6 - The typical base pay range for this role across the U.S. is USD $165,600 - $296,400 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $220,800 - $331,200 per year.

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:
https://careers.microsoft.com/us/en/us-corporate-pay


This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.



Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.

Microsoft Mountain View, California, USA Office

1065 La Avenida, Mountain View, CA 94043, Mountain View, United States, 94043

Microsoft Palo Alto, California, USA Office

Palo Alto, United States

Microsoft San Francisco, California, USA Office

835 Market Street, Suite 700, San Francisco, CA 94103, San Francisco, United States, 94103

Microsoft San Jose, California, USA Office

San Jose, United States

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Sunnyvale, United States

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