Senior Principal Engineer (PE) / Subject Matter Expert (SME) – Quartus Timing Analysis & Optimization

Altera is seeking a highly experienced Senior Principal Engineer / Subject Matter Expert (SME) to drive the architecture, development, and advancement of next-generation timing analysis, modeling, and optimization technologies within the Quartus FPGA Compiler.

This role will provide technical leadership across the Quartus compilation flow, with a particular emphasis on Static Timing Analysis (STA), timing closure, timing modeling, optimization algorithms, and scalable compiler infrastructure. The successful candidate will work closely with architecture, synthesis, fitting, routing, and timing teams to improve compiler quality of results (QoR), runtime, scalability, and signoff correlation for next-generation FPGA devices.

The ideal candidate is recognized as an industry expert in timing analysis and optimization with deep experience building high-performance EDA engines and solving complex timing convergence challenges across large-scale digital designs.

Key Responsibilities

Quartus Timing Analysis & Optimization Leadership

• Define and drive the technical roadmap for timing analysis, timing modeling, and timing optimization within the Quartus FPGA Compiler.

• Lead the design and implementation of advanced timing engines supporting FPGA compilation, placement, routing, and timing closure.

• Develop methodologies to improve timing convergence across the Quartus RTL-to-bitstream flow.

• Partner with architecture and compiler teams to enable best-in-class timing QoR and signoff correlation.

Static Timing Analysis (STA)

• Architect and develop next-generation STA capabilities, including graph-based and path-based timing analysis.

• Advance support for complex timing scenarios, including:

  • Multi-corner, multi-mode (MCMM) analysis

  • Timing exception handling

  • Clock domain crossing analysis

  • Variation-aware timing methodologies

  • Incremental timing analysis

• Improve timing accuracy while maintaining industry-leading scalability and runtime performance.

Timing Modeling & Signoff Correlation

• Develop timing modeling methodologies that accurately correlate Quartus results with silicon behavior and signoff requirements.

• Drive innovations in delay modeling, clock modeling, timing abstraction, and hierarchical timing analysis.

• Partner with FPGA architecture teams to ensure accurate representation of device resources and timing characteristics.

Compiler Algorithms & Infrastructure

• Design scalable data structures and algorithms for timing analysis and optimization.

• Improve compiler performance through parallelization, multi-threading, and incremental processing techniques.

• Drive architectural improvements that enable efficient handling of large, complex FPGA designs.

Cross-Functional Technical Leadership

• Provide technical mentorship and thought leadership across engineering teams.

• Collaborate with synthesis, placement, routing, architecture, verification, and software engineering organizations.

• Influence future FPGA compiler capabilities through technical strategy, innovation, and long-term planning.

Required Qualifications

• MS or PhD in Computer Science, Computer Engineering, Electrical Engineering, or related field.
   

• 15+ years of experience in EDA software development, timing analysis, physical design, FPGA compilation, or related domains.
   

• Deep expertise in:

  • Static Timing Analysis (STA)

  • Timing closure methodologies

  • Timing modeling and correlation

  • Physical design optimization

  • RTL-to-GDS or RTL-to-bitstream design flows

  • Multi-corner multi-mode (MCMM) analysis
     

• Strong understanding of:

  • Placement and routing algorithms

  • Clock analysis and optimization

  • Path-Based Analysis (PBA)

  • Constraint management and timing exceptions

  • Incremental timing architectures
     

• Extensive software development experience in C++ and large-scale optimization systems.
   

• Proven track record developing high-performance, highly scalable EDA engines.

Preferred Qualifications

• Direct experience developing FPGA compilation tools.
   

• Prior experience with the Quartus compiler, Timing Analyzer, Fitter, Routing, or related FPGA implementation technologies.
   

• Expertise in one or more of the following:

  • Path-based timing optimization

  • Clock-Reconvergence Pessimism Removal (CRPR)

  • Latch-based timing analysis

  • Incremental optimization frameworks

  • Timing-driven placement and routing

  • Variation-aware analysis techniques
     

• Experience designing multi-threaded or distributed EDA infrastructure.
   

• Industry-recognized technical leadership demonstrated through patents, publications, standards contributions, or major product innovations.

What You'll Bring

• Recognized subject matter expertise in timing analysis and optimization.
   

• Ability to drive complex technical initiatives from concept to production.
   

• Strong systems-thinking approach to compiler architecture and optimization.
   

• Passion for solving challenging timing closure and scalability problems.
   

• Proven ability to influence engineering direction across multiple organizations.

Impact

In this role, you will play a critical leadership position in shaping the future of the Quartus FPGA Compiler, driving innovations in timing analysis, modeling, optimization, and timing closure technologies that help customers achieve faster compilation, improved QoR, and more predictable design convergence on next-generation FPGA platforms.