Design and develop ARM-based SoC architectures, focusing on performance and power efficiency, while collaborating with cross-functional teams on IP development and integration.
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Key Responsibilities
- SoC Architecture Definition: Design and develop ARM-based System-on-Chip (SoC) architectures, ensuring optimal performance and power efficiency for markets like mobile, automotive, and infrastructure.
- IP Development & Integration: Develop Intellectual Property (IP) features.
- Micro-architecture Design: Translate high-level architectural specifications into detailed micro-architecture specifications and RTL code using SystemVerilog.
- Cross-functional Collaboration: Partner with software and hardware teams to define system-level requirements, including firmware and peripheral integration.
Required Skills & Experience
- Education: Bachelor’s or Master’s degree in Electrical Engineering or Computer Engineering.
- Architecture Knowledge: Strong understanding of ARM based SoC architecture
- Design: Proven experience in Verilog/SystemVerilog RTL design.
- AMBA Protocols: Deep knowledge of ARM AMBA protocols
The annual salary range for California is $154,000 to $286,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
We’re doing work that matters. Help us solve what others can’t.Cadence Design Systems San Jose, California, USA Office
2655 Seely Avenue, San Jose, CA, United States, 95134
Similar Jobs
Aerospace
The role involves leading the architecture development for SOC in high-performance networking, guiding custom ASIC design, collaborating across teams, and ensuring performance and integration.
Top Skills:
AsicDigital Signal ProcessingFpgaNetworking HardwareNetworking ProtocolsSilicon Architecture
Artificial Intelligence • Internet of Things • Semiconductor
Lead and manage the emulation team for SoC performance verification, develop testbenches, and collaborate with architecture teams for benchmarking.
Top Skills:
C/C++PythonRtl (SystemverilogShell ScriptingSystemcTclVerilogVhdl)
Hardware • Information Technology • Semiconductor • Manufacturing
Responsible for defining SoC architecture solutions, focusing on high-speed interfaces and power architecture while collaborating with cross-functional teams to refine requirements and optimize design.
Top Skills:
Asic Design ToolsHardware Description LanguagesPcieSimulation MethodologiesUcie
What you need to know about the San Francisco Tech Scene
San Francisco and the surrounding Bay Area attracts more startup funding than any other region in the world. Home to Stanford University and UC Berkeley, leading VC firms and several of the world’s most valuable companies, the Bay Area is the place to go for anyone looking to make it big in the tech industry. That said, San Francisco has a lot to offer beyond technology thanks to a thriving art and music scene, excellent food and a short drive to several of the country’s most beautiful recreational areas.
Key Facts About San Francisco Tech
- Number of Tech Workers: 365,500; 13.9% of overall workforce (2024 CompTIA survey)
- Major Tech Employers: Google, Apple, Salesforce, Meta
- Key Industries: Artificial intelligence, cloud computing, fintech, consumer technology, software
- Funding Landscape: $50.5 billion in venture capital funding in 2024 (Pitchbook)
- Notable Investors: Sequoia Capital, Andreessen Horowitz, Bessemer Venture Partners, Greylock Partners, Khosla Ventures, Kleiner Perkins
- Research Centers and Universities: Stanford University; University of California, Berkeley; University of San Francisco; Santa Clara University; Ames Research Center; Center for AI Safety; California Institute for Regenerative Medicine



