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Intel

SoC Debug Engineer

Posted 4 Days Ago
Be an Early Applicant
In-Office
Santa Clara, CA, USA
106K-149K Annually
Mid level
In-Office
Santa Clara, CA, USA
106K-149K Annually
Mid level
Performs low-level SoC and subsystem debugging, root-cause analysis, failure triage, bench testing, and product characterization. Develops debug tools, scripts, requirements, and design-for-debug techniques while collaborating with design, validation, and manufacturing teams to improve reliability, readiness, and debug workflows.
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Job Details:

Job Description: 

The Role and Impact

 

As a SoC Debug Engineer, you will play a pivotal role in ensuring the reliability and performance of Intel's cutting-edge products. You will perform complex debug tasks across multiple systems and subsystems, leveraging your expertise to isolate failures, resolve issues, and optimize debug processes. Your contributions will directly enhance product readiness and help deliver transformative technologies to market.


 

Business group

 

The Data Center Group (DCG) is dedicated to advancing scalable technologies that power data centers and enable the future of computing. This organization focuses on delivering innovative solutions for high-performance computing, cloud services, and enterprise systems. By joining DCG, you will be part of a team driving impactful advancements that align with Intel's broader vision for global innovation.


 

Key Responsibilities:


  • Perform detailed and low-level debug for system-on-chip (SoC) designs and subsystems across Intel products.
  • Conduct root cause analysis for triage failures and marginality issues to ensure system-wide reliability.
  • Define, develop, and implement advanced debug techniques, tools, and scripts to enhance debug efficiency.
  • Formulate debug requirements and strategies at the system level, ensuring alignment with architectural compatibility.
  • Drive bench testing for new product features and functionality while developing methodologies for improved characterization activities.
  • Collaborate with design, validation teams, and manufacturing factories to track SoC debug readiness and optimize workflows.
  • Continuously improve debugging practices through innovative design-for-debug (DFD) techniques and workflows.


The ideal candidate should show the following behavioral traits:

 

  • Strong analytical and problem-solving skills with attention to detail.
  • Effective communication skills willing to work across diverse technical teams.

Qualifications:

Minimum Qualifications are required to be initially considered for this position:


  • Bachelor's degree in Electrical Engineering, Computer Engineering, or related field

  • 3+ years of hands-on experience in:

    • SoC debugging gained through internships, academic projects, coursework, or hands-on training.
    • SoC design, architecture, firmware, and software debugging techniques.
    • Debug tools, DFD technologies, and scripting languages.


Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

 

 

Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.


  • Master's degree in Electrical Engineering, Computer Engineering or related field.
  • Interested in innovation and continuous improvement in debugging methodologies and workflows.

Your expertise and dedication will help shape the future of Intel's products and technologies. Join us to make a meaningful impact and drive innovation in the world of computing.

          

Job Type:College Grad

Shift:Shift 1 (United States of America)

Primary Location: US, Massachusetts, Beaver Brook

Additional Locations:US, Arizona, Phoenix, US, California, Santa Clara, US, Oregon, Hillsboro, US, Texas, Austin

Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.



Annual Salary Range for jobs which could be performed in the US: $105,650.00-149,150.00 USD

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

*

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
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Robert Noyce Building, Santa Clara, CA, United States, 95052

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Mountain View, United States

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San Jose, United States

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2200 Mission College Blvd. , Santa Clara, CA, United States, 95054

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