SoC Design Engineer

• Design and verify digital circuits for CMOS image sensors (CIS), including sensor array timing control logic, analog-digital interface modules, and ISP (Image Signal Processing) data pipelines, in accordance with product requirements, system architecture, and ASIC design methodology.
• Perform full-chip SoC integration, including IP integration, clock/reset domain management, power-aware design, and system-level verification to ensure functional correctness and tape-out readiness.
• Develop, integrate, and validate IPs through the complete ASIC design flow: RTL coding in Verilog/SystemVerilog, simulation, synthesis and DFT implementation.
• Conduct static timing analysis (STA) for image sensor timing-critical paths, including interfaces between analog front-end and digital control logic, ensuring robust timing closure across process corners.
• Collaborate closely with the back-end physical design team on floor planning, timing closure, power optimization, and DFT strategy throughout the implementation cycle.
• Perform pre-silicon verification using UVM-based testbenches, and scripting languages (Python, Perl) for automation, coverage analysis, and regression testing.
• Work with sensor analog/digital engineers to co-develop system-level architectures, define interface protocols, and validate mixed-signal functionality during integration and bring-up.
• Partner with algorithm engineers to implement hardware-efficient microarchitectures, develop C/C++ reference models, perform RTL-to-model co-simulation, and optimize hardware/software partitioning for imaging pipelines.
• Support post-silicon activities including chip bring-up, silicon validation, debugging, and performance tuning in collaboration with firmware, application, and image quality teams.
• Contribute to image tuning, sensor characterization, and product qualification by analyzing hardware behavior and providing feedback to algorithm and system teams.
• Create and maintain technical documentation, including architecture specifications, registers, interface control documents. 

• Architecture for Wi-Fi 6 AP transmitter.
• Wi-Fi PHY based RTL design and verification using Verilog.
• Module-level verification and full-chip integration support.
• Design optimization techniques for area, power, and timing.
• Using industry-standard digital design and verification tools.

Annual base salary for this role in California, US is expected to be between $156,853 - $160,000. Actual pay will be determined on a number of factors such as relevant skills and experience, and the pay of employees in the similar role.