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Cadence Design Systems

Sr. Principal Product Engineer

Posted Yesterday
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In-Office
San Jose, CA, USA
154K-286K Annually
Senior level
In-Office
San Jose, CA, USA
154K-286K Annually
Senior level
As a Product Engineer at Cadence, you will provide technical expertise in ASIC design, collaborate on software development, and optimize design methodologies for customer-specific goals.
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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

This opportunity is for a Product Engineer in the Digital and Signoff Group (DSG) at Cadence. The Cadence Digital and Signoff Group will offer you a dynamic environment in which you will work with innovative R&D and Customer Engagement teams to influence the development of software tools for advanced chip design platforms. As Product Engineer, you will be a source of technical place and route expertise to Cadence customers and to R&D.

You are a motivated and energetic engineer with a deep understanding of ASIC design methodologies and of every stage of the RTL to GDSII flow.
You have proven hands-on experience with timing closure and PPA optimization at 16nm and below nodes.
You combine your deep understanding with strong analysis skills to debug customer problems and propose solutions, with an organized and coherent approach.

Key Responsibilities

  • Technical Expert: Serve as the primary place-and-route (P&R) resource for internal development teams and external customers.
  • Product Evolution: Collaborate with R&D to track, diagnose, and resolve software issues, ensuring a robust tool release cycle.
  • Design Benchmarking: Execute competitive benchmarks to demonstrate Cadence’s edge in Power, Performance, and Area (PPA).
  • Flow Innovation: Develop and deploy customized RTL-to-GDSII methodologies and scripts to meet specific customer design goals.

Position Requirements

  • Education:
    • Bachelors in Electronics Engineering (EE) + 5 or more years of industry experience, OR
    • Masters in Electronics Engineering (EE) + 3 or more year of digital implementation experience.
  • Core Expertise: Deep understanding of the full ASIC design flow (RTL-to-GDSII) with a focus on physical design and timing & DRC analysis.
  • Advanced Node Experience: Proven hands-on experience with timing closure, process design rules and PPA optimization at 7nm, 5nm, or below.
  • Tool Proficiency: High familiarity with industry-standard EDA tools for  placement, routing, and signoff.
  • Scripting Skills: Proficiency in Tcl, Python, or Perl (familiarity with AI-driven productivity tools is a major plus).
  • Communication: Strong verbal and written skills to translate complex technical issues into actionable solutions.

The annual salary range for California is $154,000 to $286,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

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Cadence Design Systems San Jose, California, USA Office

2655 Seely Avenue, San Jose, CA, United States, 95134

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