Designs, simulates, verifies, and refines multi-gigabit PAM4 SerDes IP and analog/mixed-signal receiver blocks, including TI-SAR ADCs, CTLE, DFE, and AFE components. Responsibilities include CDR development, high-speed testing with oscilloscopes and BERT, analog-digital interface verification, layout optimization, clock and synchronization design, and IP documentation. The engineer collaborates with system and test teams on high-speed interfaces, packages, boards, and system clocks for image sensor and bridge chip products.
Overview :
Responsible for design, development, and refinement of Multi-Gbps PAM4 SerDes IP. Design and debug experience on RTL level signal synchronization, clock tree and cross domain clock designs is a significant plus.
Responsible for design, development, and refinement of Multi-Gbps PAM4 SerDes IP. Design and debug experience on RTL level signal synchronization, clock tree and cross domain clock designs is a significant plus.
Need to work closely with system and test engineers to develop high speed interface, package/board, and system clocks in image sensor and bridge chip products.
Responsibilities :
• Analog/Mixed-Signal design, simulation and verifications esp PAM4 receiver designs such as TI-SAR ADC, CTLE/DFE and other blocks in AFE.
• CDR design experience is significant plus.
• High speed test with scope and BERT.
• Layout design and support. Need to get involved into layout optimizations for high speed or high precision performance directly.
• Interface verifications between analog and digital.
• IP and design spec documentations.
• Analog/Mixed-Signal design, simulation and verifications esp PAM4 receiver designs such as TI-SAR ADC, CTLE/DFE and other blocks in AFE.
• CDR design experience is significant plus.
• High speed test with scope and BERT.
• Layout design and support. Need to get involved into layout optimizations for high speed or high precision performance directly.
• Interface verifications between analog and digital.
• IP and design spec documentations.
Requirements :
• Familiar with Cadence analog design/layout flow and spice/spectreMDL simulations.
• Masters of Electrical Engineering or PhD with 3+ yrs of expertise.
• Familiar with Cadence analog design/layout flow and spice/spectreMDL simulations.
• Masters of Electrical Engineering or PhD with 3+ yrs of expertise.
Annual base salary for this role in California, US is expected to be between $150,000 - $250,000. Actual pay will be determined on a number of factors such as relevant skills, education, experience, and the pay of employees in the similar role.
OMNIVISION Santa Clara, California, USA Office
4275 Burton Dr, Santa Clara, California, United States, 95054 1512
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