Transmitter (Tx) SerDes Design Lead — 224G/448G

Ciena’s WaveLogic family of products enables high-speed optical transmission solutions that are foundational to modern telecommunications networks. This role contributes to the continued advancement of high-speed circuit design for broadband fiber-optic systems within a vibrant team with a proven track-record of success over 30 years of evolution in high-speed circuits for broadband fiber-optic modems — the team that pioneered the world's first high-speed DAC and ADC analog macros for coherent fiber-optic products.  

We are looking for a hands-on Transmitter (Tx) SerDes Design Lead to design and deliver our high-speed electrical transmitter macros for 224G and 448G SerDes in the latest deep-submicron CMOS technologies.  

How you will make an impact: 

• Own schematic-level design and post-layout verification of the transmitter signal chain and it’s blocks: DAC-based output stage, serialization, clocking interface, and output driver 

• Work closely with management, system designers, and lab validation teams to evolve the architecture and meet standard and product requirements 

• Evaluate circuit topologies and recommend implementations based on tradeoffs across power, area, bandwidth, and technology constraints. 

• Collaborate with layout and design engineers to deliver designs through full GDSII integration. 

• Drive extraction-based post-layout simulations and validate transmitter performance (bandwidth, linearity/RLM, return loss, jitter, and power) across process, voltage, and temperature conditions. 

• Own root-cause analysis of design- and post-layout performance gaps and implement the corrective design actions to meet specifications.   

• Maintain block- and transmitter-level performance and power tracking against the agreed targets.  

• Translate agreed architecture and system requirements into the transmitter implementation, and feed design and silicon learnings back to inform the next architecture step.  

• Build and use behavioral/design models (e.g., MATLAB, Verilog-A) to support topology tradeoffs and specification alignment.  

• Partner with lab validation teams to correlate silicon results with simulations and support test-chip, product bring-up and characterization. 

• Provide technical guidance and mentorship to more junior design and layout engineers, and report status and share experience with the group on a regular basis.  

The must haves: 

• Education: Bachelor’s degree in Electrical Engineering or Computer Engineering, or applicable scientific discipline. 

• Experience: 10+ years of industrial experience designing high-speed analog, mixed-signal, or SerDes transmitter circuits in advanced CMOS technologies, including schematic design through post-layout verification. 

• Application of transmitter circuit building blocks including DAC-based output stages, serializers or multiplexers, output drivers, and clocking circuits. 

• Execution of post-layout and extraction-based simulations to validate performance across process, voltage, and temperature conditions. 

• Delivery of analog circuit designs through silicon validation. 

• Utilization of Cadence, Mentor, or Synopsys tools including Virtuoso, Calibre, STAR-RC, and MMSIM. 

• Demonstrated written and verbal communication skills and ability to work independently and within a team environment. 

Nice to haves: 

• Experience: Application of 224G or 448G PAM4 or PAM6 SerDes and related OIF-CEI or IEEE standards. 

• Experience contributing to transmitter architecture using MATLAB, Verilog-A, or C++. 

• Application of signal integrity, power integrity, channel, and package co-design methodologies, including use of EM tools such as HFSS or EMX. 

• Experience mentoring engineers within analog macro design teams. 

• Experience with mixed-signal validation using high-speed measurement and probing equipment.