Lead physical design solutions from synthesis through GDS and tape-out for complex HPC devices. Drive floorplanning, placement, routing, clock construction, timing, power, IR/EM, and physical verification closure. Improve design tools, flows, and methodologies while optimizing power, performance, and area. Collaborate with RTL, DFT, architecture, and R&D teams across advanced technology nodes to deliver high-quality SoC designs.
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Cadence is the leader in hardware emulation-acceleration technologies and products. As a Physical Design Architect you will drive solutions for complex designs from synthesis to GDS through tape-out. You are knowledgeable about floorplan, clock construction, placement, routing, and signoff closure activities such as timing analysis, physical verification, and IR/EM. You have exceptional communication skills and can collaborate with partner RTL, DFT, and Architecture teams. As a senior engineer, you will contribute to further developing our tools and flows to improve design quality and execution.
Our emulation-acceleration system platform is the most advanced industry-leading configurable scalable system, generation after generation, used in labs and datacenters. At the heart of these systems are a multitude of interconnected highly complex high-performance computing (HPC) devices based on a proprietary Boolean processor architecture. This is a role in the core technology team.
Key Responsibilities:
The duties and responsibilities include:
- Drive solutions in logic synthesis, floorplan, place and route (PNR), clock construction
- Provide continuous improvement to existing tools, flows, and methodologies
- Optimize power, performance, and area to meet design requirements
- Experience with advanced process nodes and technologies
- Collaborate closely with cross functional teams to ensure proper design execution
- Work with R&D teams to improve Cadence’s suite of tools
- Close designs adhering to timing, power, IR/EM, and foundry specifications
Qualifications
- BS with a minimum of 15 years of experience OR MS with a minimum of 10 years of experience OR PhD with a minimum of 7 years of experience
- Successfully owned and driven blocks/SoCs to tape-out
- Comfortable in the latest advanced technology nodes
- Experience in at least one scripting language like PERL, Python, TCL, or Shell is preferred
- Self-motivated, team player with strong problem-solving skills to collaborate with teams to deliver results
- Excellent written and verbal communication skills
- BS/MS with 10-15+ years of relevant hands-on experience in physical design
Cadence Design Systems San Jose, California, USA Office
2655 Seely Avenue, San Jose, CA, United States, 95134
Cadence Design Systems Santa Clara, California, USA Office
Santa Clara, United States
Cadence Design Systems Sunnyvale, California, USA Office
Sunnyvale, United States
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