Astera Labs Logo

Astera Labs

Principal Emulation Engineer

Posted 3 Days Ago
Be an Early Applicant
In-Office
San Jose, CA, USA
207K-230K Annually
Expert/Leader
In-Office
San Jose, CA, USA
207K-230K Annually
Expert/Leader
Architects and maintains ASIC and SoC emulation environments for pre-silicon validation. Integrates RTL, transactors, protocol models, software, and test infrastructure for hardware-software co-simulation. Verifies PCIe, Ethernet, memory, storage, and other interfaces; develops reusable models, tests, checkers, and debug methods; analyzes coverage and performance; and leads cross-functional debugging across design, verification, firmware, and systems teams.
The summary above was generated by AI

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Principal Emulation Engineer — San Jose, CA 

Role Overview 

As a Principal Emulation Engineer, you will build and operate emulation environments that let verification teams stress-test complex ASICs before silicon. You’ll partner closely with design, verification, firmware, and systems engineers to model hardware-software interactions, exercise high-speed protocols, and isolate issues across RTL, transactors, test environments, and code. Your hands-on leadership will turn difficult debug problems into actionable fixes and improve confidence in each product milestone. 

Astera Labs is accelerating the infrastructure behind AI by delivering purpose-built connectivity solutions for rack-scale systems. In this role, you’ll help validate the switching, PCIe, Ethernet, memory, and storage interfaces that connect the compute fabric—enabling faster bring-up, stronger interoperability, and more reliable platforms as the company scales. 

Key Responsibilities 

  • Emulation and Prototyping 
  • Architect, build, and maintain emulation environments for complex ASICs and SoCs. 
  • Integrate RTL, transactors, protocol models, software, and test infrastructure to enable meaningful hardware-software co-simulation. 
  • Enable verification teams to stress-test designs with scalable, repeatable emulation workflows. 
  • Develop reusable models, utilities, and debug methodologies that accelerate pre-silicon validation. 
  • Protocol and SoC Verification 
  • Verify hardware-software interfaces and system behaviors in partnership with logic designers, firmware engineers, and verification teams. 
  • Exercise and debug PCI Express Gen 3 and above, Ethernet, DDR, NVMe, SPI, I2C/I3C, and similar interfaces. 
  • Analyze protocol behavior, functional coverage, performance, and corner cases across complex server, storage, and networking systems. 
  • Translate system requirements into practical emulation scenarios, tests, checkers, and measurable verification goals. 
  • Debug and Technical Leadership 
  • Debug design, environment, transactor, software, and test-code issues across the emulation stack. 
  • Identify software and hardware co-simulation limitations and apply effective isolation and debug techniques. 
  • Partner with cross-functional teams to prioritize a dynamic workload, resolve issues quickly, and drive risks to closure. 
  • Provide technical leadership, communicate clearly, and operate effectively with minimal guidance and supervision. 

Basic Qualifications 

  • Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field. 
  • 8–12 years of experience supporting or developing complex SoC or silicon products for server, storage, or networking applications. 
  • Experience working with logic designers to architect, specify, and verify hardware-software interfaces on complex SoCs. 
  • Working knowledge of PCI Express Gen 3 or later, CXL, UALink, Ethernet, DDR, NVMe, SPI, I2C/I3C, or similar communication protocols. 
  • High proficiency in SystemVerilog and hardware verification environments. 
  • Experience understanding software and hardware co-simulation limitations and applying effective debug methods. 
  • Programming and scripting experience in Python, Perl, C, or similar languages. 
  • Professional, entrepreneurial, and open-minded approach with a can-do attitude, strong prioritization skills, and a customer-focused mindset. 
  • Authorized to work in the United States and available to start immediately. 

Preferred Qualifications 

  • Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field. 
  • Hands-on experience with Palladium, Zebu, Veloce, HAPS, FPGA prototyping, or similar emulation and prototyping technologies. 
  • Experience developing models for emulation and prototyping and working in non-UVM verification environments. 
  • Experience building protocol transactors, behavioral models, software drivers, or system-level validation infrastructure. 
  • Based in the San Jose area or open to relocation; comfortable working fully in person. 

Salary range is $207,000 to $230,000 depending on experience, level, and business need. This role may be eligible for discretionary bonusincentives and benefits. 


We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

HQ

Astera Labs San Jose, California, USA Office

San Jose, CA, United States

Similar Jobs

12 Days Ago
In-Office or Remote
7 Locations
230K-323K Annually
Expert/Leader
230K-323K Annually
Expert/Leader
Aerospace
Build Blue Origin’s pre-silicon emulation and FPGA prototyping capability from the ground up. Define platform strategy, select hardware, develop build and release flows, and operate nightly image services. Lead FPGA implementation, RTL adaptation, timing closure, hardware-in-the-loop integration, platform debugging, capacity planning, and user support. Collaborate with DSP, RF, antenna, verification, and architecture teams to validate satellite communications hardware and scaled beamforming datapaths.
Top Skills: ArmC++CiDdrDpiDspEthernetFpgaHapsJesd204B/CLdpc/FecPalladiumPcieProtiumPythonRf InstrumentationSce-MiSystemverilogTclVeloceVerilogZebu
24 Days Ago
In-Office
San Jose, CA, USA
210K-280K Annually
Senior level
210K-280K Annually
Senior level
Artificial Intelligence • Hardware • Machine Learning • Natural Language Processing • Software • Generative AI
Own hardware emulation models and platform infrastructure for next-generation AI accelerator chips. Build transactors, behavioral and memory models using SystemVerilog and C/C++, ensure RTL and IP are emulation-ready, and automate continuous regression testing. Lead emulation flows, partitioning, performance tuning, vendor relationships, and platform capacity. Support software bring-up, performance verification, functional regression acceleration, and silicon debug while providing technical leadership across design, verification, and software teams.
Top Skills: CC++Cadence PalladiumClaudeDdrEthernetFpga PrototypingHbmPciePythonShellSiemens VeloceSynopsys ZebuSystemverilog
20 Days Ago
In-Office
San Jose, CA, USA
179K-332K Annually
Senior level
179K-332K Annually
Senior level
Artificial Intelligence • Cloud • Hardware • Software • Semiconductor
Architect, design, bring-up, and sustain emulation-acceleration hardware system platforms. Lead design reviews, set hardware standards, mentor junior engineers, ensure SI/PI and manufacturability, and drive cross-functional development from concept to production.
Top Skills: Board Bring-UpBoard-Level Hardware DesignHigh-Speed InterfacesPcb LayoutPower Integrity (Pi)Power ManagementSchematic Capture SoftwareSignal Integrity (Si)

What you need to know about the San Francisco Tech Scene

San Francisco and the surrounding Bay Area attracts more startup funding than any other region in the world. Home to Stanford University and UC Berkeley, leading VC firms and several of the world’s most valuable companies, the Bay Area is the place to go for anyone looking to make it big in the tech industry. That said, San Francisco has a lot to offer beyond technology thanks to a thriving art and music scene, excellent food and a short drive to several of the country’s most beautiful recreational areas.

Key Facts About San Francisco Tech

  • Number of Tech Workers: 365,500; 13.9% of overall workforce (2024 CompTIA survey)
  • Major Tech Employers: Google, Apple, Salesforce, Meta
  • Key Industries: Artificial intelligence, cloud computing, fintech, consumer technology, software
  • Funding Landscape: $50.5 billion in venture capital funding in 2024 (Pitchbook)
  • Notable Investors: Sequoia Capital, Andreessen Horowitz, Bessemer Venture Partners, Greylock Partners, Khosla Ventures, Kleiner Perkins
  • Research Centers and Universities: Stanford University; University of California, Berkeley; University of San Francisco; Santa Clara University; Ames Research Center; Center for AI Safety; California Institute for Regenerative Medicine

Sign up now Access later

Create Free Account

Please log in or sign up to report this job.

Create Free Account