Develop and maintain UVM-based RTL verification environments for ASIC DFT logic. Create coverage-driven plans, directed tests, assertions, and automated regressions; verify MBIST, scan, ATPG, JTAG, boundary scan, and other DFT functionality. Debug simulation and design issues, validate gate-level behavior and tester patterns, support SoC-level and post-silicon bring-up, and collaborate with DFT design and manufacturing engineers to deliver reliable silicon.

Own complex ASIC and SoC physical implementation from synthesized netlist through signoff, including floorplanning, placement, CTS, routing, timing closure, ECOs, physical verification, and power integrity. Lead cross-functional timing and implementation convergence, develop automation and methodologies, resolve advanced-node challenges, and provide technical mentorship. Partner with RTL, architecture, DFT, verification, package, and SI/PI teams while driving PPA, runtime, quality, and tapeout readiness.

Delos is a stealth-mode startup seeking to build foundational technology for AI data centers, fostering a collaborative and responsible working environment.