Top Tech Jobs & Startup Jobs in San Francisco Bay Area, CA

Design and validate high-speed packages, develop EDA tools and automation flows, model package structures, and ensure consistency in design processes.

The Optoelectronics & Integration Researcher will conduct research on high-speed optoelectronic interfaces, collaborate with Nokia Bell Labs, and define materials and techniques for optical subassemblies.

Serve as the primary technical resource for the Eastern U.S. sales team, driving technical evaluation, delivering presentations and demos, responding to RFIs/RFPs, producing quotes, providing post-sales support, mentoring team members, and engaging at industry events to align Nokia optical and transmission solutions with customer needs.

Lead development and qualification of production PIC test capability, own tester qualification, drive test efficiency/capacity improvements, execute engineering change notices, participate in quality review boards, and collaborate with PIC design, fab, and module teams at the South San Francisco facility.

Simulate and optimize ultra high-speed PCB channels (112G+ SerDes), guide digital hardware designers using simulation and measurements, design PCB test boards, document results, participate in design reviews, and improve SI processes while collaborating cross-functionally.

The NI IP Commercial Manager will lead commercial strategies, manage approvals, advise stakeholders, oversee commitments, and support negotiations throughout the sales cycle.

The role involves generating high-quality analog circuit layouts using advanced CAD tools, optimizing designs, and collaborating with circuit designers while ensuring adherence to stringent requirements.

Lead procurement support for IP Hardware Engineering across NPI and product launches. Manage supplier relationships, negotiate component pricing and contracts, perform BOM analysis and risk mitigation, and coordinate cross-functional readiness and shortage escalations to meet schedule and cost targets.

Develop and optimize UE Layer 2 and Layer 3 protocol stack (MAC, RLC, PDCP, RRC, NAS) for LTE and 5G NR. Implement 3GPP features, debug with protocol analyzers, integrate with PHY/L1, run functional and performance tests using UE simulators and network emulators, and ensure operator compliance.

The role involves developing and verifying SoCs using ASIC and FPGA technologies, creating test plans, and debugging with team collaboration.