Top Tech Jobs & Startup Jobs in San Francisco Bay Area, CA

Build scalable tools and workflows for analyzing and optimizing AI training and inference performance. Integrate profiling infrastructure with AI frameworks, identify workload bottlenecks, automate diagnosis, and translate engineers’ needs into intuitive tooling. Collaborate with performance engineers, hardware architects, and software teams to align profiling capabilities with real-world workloads.

Design, develop, test, and optimize system software for next-generation ARM-based SoCs across pre- and post-silicon phases. Analyze architectural bottlenecks, workload performance, and performance-per-watt tradeoffs; develop hardware/software policies and optimization strategies. Lead performance analysis, competitive benchmarking, architecture documentation, and adoption of improvements across NVIDIA software products and open-source SDKs.

Develop and optimize the open-source Triton compiler for high-performance AI workloads on NVIDIA GPUs. Design compiler technology using MLIR, generate efficient low-level GPU code, tune kernels with inline PTX, analyze hardware architectures, and optimize advanced AI algorithms and numerics. Collaborate with hardware architects and CUDA compiler teams while applying parallel programming, computer architecture, assembly, and performance debugging expertise.

Provide technical mentorship to customers adopting NVIDIA’s GenAI stack, build and deploy agentic AI solutions, create demonstrations and proofs of concept, deliver technical workshops, develop industry collateral, and collaborate with engineering, product, and sales teams to secure design wins. The role focuses on optimizing and deploying large language models, leveraging GPU clusters, inference engines, cloud platforms, and AI development frameworks.

Lead design and implementation of security systems and controls for large-scale AI and HPC cluster infrastructure. Drive incident response, risk assessment, system hardening, governance, audit readiness, and cross-team collaboration to protect hardware, software, and datacenter platforms.

Build AI-driven compiler intelligence for production compiler pipelines. Design compiler optimization workflows, develop learning-based decision systems, integrate LLMs with compiler infrastructure, and validate performance across workloads. Collaborate with compiler, architecture, and performance teams to deploy reliable, scalable solutions that improve runtime, compile time, and efficiency.

Design and optimize power-efficient ASIC, GPU, and processor hardware for mobile, embedded, and datacenter platforms. Develop power metrics, drive power reductions, and deliver verified RTL meeting performance, area, and power targets. Collaborate with architects, designers, verification engineers, and VLSI teams on high-performance designs.

Define high-level SoC subsystem and I/O architecture for LPU products, translate product requirements into architecture and IP specifications, build and validate functional/architectural models (C++, SystemC, Python), and drive tradeoffs across performance, power, reliability, and security while coordinating with IP, firmware, software, RTL, verification, and post-silicon teams.

Design and simulate analog/digital circuits and power delivery networks (die to platform) for processors. Perform block- and system-level simulations, ensure reliability/performance, mentor junior engineers, and collaborate globally to improve netlist and timing quality.

Lead hardware-software co-design for LLM inference: drive and document architecture, build executable C++ hardware models, optimize performance with good algorithms and parallelism, diagnose cross-team chip and subsystem issues, and automate workflows to improve efficiency.