Integrates first-party and third-party IP into subsystems and SoCs using Verilog and SystemVerilog. Performs synthesis, timing constraint development, floor-planning analysis, performance optimization, register integration, and design-quality closure through CDC, lint, and RDC checks. Communicates project progress to customers, supports process improvements, resolves complex problems independently, and provides informal guidance to junior staff.

Integrates first-party and third-party IP into subsystems and SoCs using Verilog and SystemVerilog. Responsibilities include fabric generation, synthesis, timing constraints, floor-planning considerations, performance optimization, register integration, CDC, lint, RDC, and design-quality closure. The engineer independently resolves complex problems, supports junior staff, improves processes, and communicates progress and technical status to customers.