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Develop and maintain the high-performance C++ application for an FPGA-hosted hardware emulation framework. Collaborate with FPGA RTL designers, compiler developers, and RISC-V engineers to enable fast, debuggable, and cost-effective emulation for software and hardware co-design.

Develop and maintain core tools for microprocessor design, including simulation and build tools. Requires systems-level programming and tool validation experience.

Lead a performance engineering team to research and develop high-performance processor architectures, defining targets and guiding implementation in RTL, while analyzing performance bottlenecks.

Develop and deploy methodologies for measuring and analyzing power consumption of SiFive IPs. Guide teams in designing energy-efficient IPs through power modeling and analysis.

The intern will join the Design Verification Infrastructure team to develop and maintain the Verification Platform, enhancing design verification technologies through collaboration and software development in Scala and Python.

Lead a performance engineering team to research, model, and develop high-performance core architectures and microarchitectures. Design experiments, identify HW/SW bottlenecks, and work with design teams to implement and deliver performance targets in RTL and FPGA flows.

Research, model, and develop microarchitecture features for high-performance RISC-V processors. Design and run experiments, identify HW/SW performance bottlenecks, perform workload characterization and reduction, and collaborate with design teams to implement and deliver performance targets in RTL and FPGA prototypes.

Lead a performance engineering team to research, model, and develop high-performance CPU core architectures. Design experiments, analyze HW/SW performance bottlenecks, and work with design teams to implement and deliver RTL targets.

Develop and maintain a scalable Verification Platform: extend Chisel/CIRCT, build Scala libraries and Python tools for test harnesses, stimulus, and metadata querying, support end-to-end verification flows, and educate DV teams on best practices.

As a Datacenter System Software Architect at SiFive, you'll design RISC-V Linux systems for datacenters, engage with customers, and optimize performance across software and hardware.