Top Tech Jobs & Startup Jobs in San Francisco Bay Area, CA

Architect and build TeraWave Point of Presence infrastructure, implement and optimize wire-speed dataplane using DPDK/VPP, tune IP networking stacks (BGP/OSPF), drive performance engineering at the software-hardware interface, mentor engineers, and integrate PoP systems with the broader satellite communications ecosystem.

Lead RTL-to-GDS physical implementation of SoCs for space applications, perform signoff closure (STA, PV, LEC, EM/IR), debug timing, integrate mixed-signal verification, develop PV runsets and flow automation, implement DFT, collaborate with front-end and analog teams, interface with foundries, and support post-silicon validation.

Design and layout complex multi-layer PCBs for mmWave/RF, high-speed digital, mixed-signal, and high-power systems. Perform stackup and routability studies, signal integrity analysis, create DRCs and fabrication/assembly documentation, work with fabricators/CMs, support board bring-up and space-environment design considerations.

Lead the design and development of mixed-signal subsystems, focusing on architecture, specifications, modeling, and integration for advanced communication and data conversion SoCs.

Lead the design and implementation of high-performance PoP infrastructure, optimize networking software, and mentor engineering teams at Blue Origin.

Own signal and power integrity for RF/mixed-signal and mmWave IC packaging. Perform HFSS and EM simulation for high-speed signals and PDNs, model and characterize RF/mmWave packages, collaborate with RFIC/mmWave/ASIC/SoC and package layout teams, lead SI/PI package delivery, and produce documentation and specifications supporting design reviews.

Lead end-to-end ASIC/SoC design and verification for TeraWave RFIC/ASICs, from requirements and RTL through FPGA/silicon bring-up. Responsibilities include complex subsystem and SoC verification, DSP/modem design, ARM integration, high-speed interface integration, performance/power optimization, backend support (DFT/STA), formal verification, and post-silicon validation.

Design and develop RFICs and mixed-signal ASICs using Cadence Virtuoso and Spectre RF. Build analog models and verification methodologies, create and execute pre/post-silicon test plans, trade off noise/linearity/power, support lab integration and troubleshooting, resolve layout and timing issues, collaborate with systems/firmware/architecture teams, and adopt AI-based methods across design, simulation, verification, characterization, and manufacturing.

Lead design and development of modem PHY IP for Terawave ASIC and prototypes. Translate algorithms into hardware architectures, build bit-accurate models, perform trade studies, define interfaces, support FPGA/silicon bring-up, collaborate with systems/ASIC/RF/verification teams, and analyze simulation/emulation/lab/silicon data to improve PHY performance and validation.

Lead verification of modem PHY IP: define strategies, build block/subsystem verification environments, create testbenches and coverage, correlate RTL with reference models, debug RTL and integration issues, support emulation/FPGA/prototyping and post-silicon debug, and drive regression automation and CI for high-throughput wireless ASIC platforms.