Top Tech Jobs & Startup Jobs in San Francisco Bay Area, CA

Lead design and ownership of system-level integration and test architecture for a satellite communications constellation. Define test strategy, build progressive integrated test facilities (link-level to full-system), integrate ground terminal validation, embed tests in CI/CD pipelines, size and procure major test infrastructure, and collaborate across payload, satellite, and network teams to ensure end-to-end validation, regulatory compliance, and production-scale acceptance testing.

Lead DFX strategy for mechanical systems from concept to high-rate production. Drive DFM/DFA/DFR/DFC, tolerance analysis, GD&T, DOE, NPI, factory automation, failure analysis, and supplier readiness. Recruit and grow a global DFX team, establish assembly processes across multiple disciplines, and define DFX review gates and metrics to improve yield, reliability, and cost.

Design and develop mechanical hardware for the TeraWave satellite constellation and ground systems. Perform structural and thermal analyses, create CAD models/drawings/BOMs, support integration and environmental testing, apply GD&T, lead design reviews, mitigate risks, and collaborate with systems, electrical, manufacturing teams and suppliers.

Lead end-to-end hardware architecture for a phased-array satellite user terminal: define system block diagrams, select SoCs and high-speed components, resolve RF/electrical/mechanical interfaces, design power/thermal systems for beamforming, drive manufacturability with CMs, and establish validation and global compliance (FCC/CE/ETSI).

Lead design and development of user terminal hardware for a high-capacity satellite network. Integrate high-speed digital logic with phased-array antennas, design HDI PCBs and power delivery, route high-speed buses (PCIe/Ethernet/MIPI/SerDes), perform EMI/noise simulations, and own hardware bring-up, debugging, and system-level testing through product lifecycle.

Lead design and implementation of a custom MAC layer for a satellite constellation. Develop TDMA/DAMA schedulers, ARQ/AMC, handover logic, and optimize interfaces to high-speed packet engines (DPDK/VPP). Collaborate with PHY and network architects, drive MAC architecture decisions, and lead protocol development from simulation through hardware integration and field testing.

Lead design, simulation, fabrication, testing, and integration of high-performance phased-array and reflector antenna systems (Q/V/E-band) for a LEO/MEO satellite constellation. Own EM simulations, prototype development, anechoic chamber measurements, environmental qualification, and cross-discipline collaboration from concept through production readiness.

Lead end-to-end software architecture for a multi-orbit satellite communications constellation, spanning flight and ground systems. Own system interfaces, program-wide CI/CD, over-the-air update strategy, configuration/version management, and cross-domain standards. Drive risk assessments, scalability, resilience, and adoption of common tools while mentoring engineers and aligning architecture with hardware constraints and verification/validation needs.

Design and develop RF payload hardware for a high-capacity satellite communications constellation. Lead HDI PCB layout, power delivery design, EMI/crosstalk mitigation, hardware bring-up and lab debugging, and integrate high-speed digital logic with phased-array antenna systems through testing and lifecycle support.

Lead the technical vision for product integrity across reliability, thermal, structural, materials, and qualification. Pioneer physics-of-failure methods, predictive reliability and AI-driven engineering, define testing/validation frameworks, mentor technical leaders, and align cross-disciplinary teams to ensure hardware survives launch and long-duration space deployment.