Top Tech Jobs & Startup Jobs in San Francisco Bay Area, CA

18 Days AgoSaved
In-Office or Remote
7 Locations
213K-299K Annually
Senior level
213K-299K Annually
Senior level
Aerospace
Lead mixed-mode design verification methodology for complex SoCs. Define co-simulation EDA environment, create Verilog/SystemVerilog testbenches and behavioral models, support analog/digital teams, and perform AMS simulations for block- and chip-level verification.
Top Skills: AmsCadence VirtuosoCmosEdaFinfetMatlabPythonSystemverilogVerilog
18 Days AgoSaved
In-Office or Remote
7 Locations
264K-370K Annually
Senior level
264K-370K Annually
Senior level
Aerospace
Lead design and ownership of system-level integration and test architecture for a satellite communications constellation. Define test strategy, build progressive integrated test facilities (link-level to full-system), integrate ground terminal validation, embed tests in CI/CD pipelines, size and procure major test infrastructure, and collaborate across payload, satellite, and network teams to ensure end-to-end validation, regulatory compliance, and production-scale acceptance testing.
Top Skills: Anechoic ChambersCi/CdFactory Acceptance TestFcc Radiating TestsFree-Space Optical (Fso)Hardware-In-The-Loop (Hil)Link EmulationMotion Control SystemsRf Signal SimulatorsTest AutomationThermal CyclingThermal Vacuum
Reposted 18 Days AgoSaved
In-Office or Remote
7 Locations
198K-277K Annually
Senior level
198K-277K Annually
Senior level
Aerospace
The Senior ASIC Design Engineer leads complex digital IP design for space communication ASICs, collaborates with teams, mentors junior engineers, and ensures high-quality delivery of silicon designs.
Top Skills: AsicDigital Signal ProcessingFpgaHigh-Speed Interface DesignRtl DesignSystem VerilogVerilog
Reposted 18 Days AgoSaved
In-Office or Remote
7 Locations
231K-323K Annually
Senior level
231K-323K Annually
Senior level
Aerospace
Lead the design infrastructure for space-based communications, manage EDA tools, support hardware design processes, and improve automation.
Top Skills: Cloud-Based Eda SolutionsEda ToolsPdksPerlPythonRtl-To-Gdsii Design FlowShell ScriptingTclVersion Control
20 Days AgoSaved
In-Office or Remote
7 Locations
249K-349K Annually
Senior level
249K-349K Annually
Senior level
Aerospace
Lead execution of complex ASIC/SoC programs from architecture through tapeout, ensuring alignment across teams and managing risks.
Top Skills: AsicCadDftFirmwareRtlSilicon DevelopmentSoc
22 Days AgoSaved
In-Office or Remote
7 Locations
231K-323K Annually
Expert/Leader
231K-323K Annually
Expert/Leader
Aerospace
Develop algorithms and models for TeraWave's custom silicon and RF systems, design advanced digital systems, and collaborate with various teams for implementation and validation.
Top Skills: C/C++DspMatlabMixed Signal DesignsRfSystem C
Reposted 23 Days AgoSaved
In-Office or Remote
7 Locations
231K-323K Annually
Senior level
231K-323K Annually
Senior level
Aerospace
Lead the IC packaging team to develop advanced packaging solutions, manage product cycles, and ensure design for manufacturability while collaborating on simulations and qualifications.
Top Skills: 2.5D/3D Em SimulatorsAntenna In PackageCadence Allegro ApdEda Cad ToolsEmxHfssIc Packaging TechnologiesMmwaveMomentumSystem In Package
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