Top Tech Jobs & Startup Jobs in San Francisco Bay Area, CA

As a Verification Engineer, you will lead the verification of Serdes by developing AMS SystemVerilog models, collaborating with the design team, and ensuring model quality.

As a Digital Design Engineer at Eliyan, you will design and develop Ethernet PCS/PMA IPs, optimize digital designs, and collaborate on high-performance products.

Lead ASIC and platform development, manage cross-functional teams, oversee project timelines, budgets, and vendor relationships to ensure successful program delivery.

The Staff DFT Engineer will define and implement DFT strategies and methodologies, work with cross-functional teams, and support device bring-up for high-volume manufacturing.

Lead and scale a design verification team for PHY and controller products. Define verification strategy and methodology (UVM, AMS, formal), drive verification planning and execution across link layer, PCS, PMA, and FEC, integrate analog models into digital flows, manage tapeout verification milestones, improve verification infrastructure and CI/CD, ensure standards compliance, and oversee vendor VIPs and firmware co-simulation for tapeout readiness.

As a Staff Digital Verification Engineer, develop verification plans, maintain test environments, and ensure compliance with Ethernet standards while leading junior engineers.

The Senior Staff Physical Verification Engineer leads all physical verification activities including DRC, LVS, and DFM for advanced chip designs, ensuring compliance across multiple foundries and technologies.

Lead architecture and RTL implementation of high-speed SerDes digital IP (224G/448G PAM4), including DSP equalization, CDR, FEC, PHY control, RTL quality, AMS integration, tapeout coordination, standards work, firmware interfaces, and post-silicon debug.

The Chief Optical Engineer will focus on bridging optical behavior with electrical IC design, leading customer engagements, and guiding production architecture for AI infrastructure.

Lead the verification of Serdes systems, develop UVM/SV testbenches and test cases, and mentor junior engineers while ensuring design quality and integration.