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Reposted 22 Hours AgoSaved
In-Office or Remote
7 Locations
Senior level
Senior level
Information Technology • Manufacturing
As a Signal and Power Integrity Engineer, you'll develop packaging solutions for chiplet interconnects, optimizing performance through simulation, measurement, and collaboration with cross-functional teams.
Top Skills: AdsAllegroHfssHspicePowerdcPowersiQ3DSiwaveSpectre
Reposted 2 Days AgoSaved
In-Office or Remote
9 Locations
Expert/Leader
Expert/Leader
Information Technology • Manufacturing
Lead firmware development for chiplet-based systems focusing on PHYs and Controllers. Manage cross-functional teams and ensure production quality. Innovate and implement methodologies for testing and deployment.
Top Skills: CC++CmisDdrEthernetIoPciePhySerdes
Reposted 2 Days AgoSaved
In-Office or Remote
9 Locations
Senior level
Senior level
Information Technology • Manufacturing
Lead the frontend digital design of D2D PHY for chiplet systems, optimizing performance and collaborating across teams while mentoring junior designers.
Top Skills: Cadence GenusCxlDdr4Ddr5PciePerlPythonSdcSerdesStaSynopsys DcSystemverilogTclUcieUpf
Reposted 6 Days AgoSaved
In-Office or Remote
7 Locations
8-12 Annually
Senior level
8-12 Annually
Senior level
Information Technology • Manufacturing
Lead STA signoff processes for complex ASIC designs, defining methodologies and collaborating with design teams to ensure timing closure and optimal performance.
Top Skills: Samsung 3NmSdcStaTclTsmc 3Nm
Reposted 6 Days AgoSaved
In-Office or Remote
7 Locations
Senior level
Senior level
Information Technology • Manufacturing
As a Principal Physical Design Engineer, you will lead ASIC development from RTL to GDSII, oversee design flow optimization, and ensure the delivery of high-performance products.
Top Skills: AsicEmGdsiiIrPnrPvRtlSamsungStaTsmc
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Reposted 6 Days AgoSaved
In-Office or Remote
7 Locations
Senior level
Senior level
Information Technology • Manufacturing
The role involves leading the physical design of ASICs, overseeing all phases from RTL to GDSII, and enhancing design methodologies.
Top Skills: AntennaAsicDrcEmGdsiiIrLvsPnrRtlSta
Reposted 8 Days AgoSaved
In-Office or Remote
9 Locations
5-5 Annually
Senior level
5-5 Annually
Senior level
Information Technology • Manufacturing
As a Digital Design Engineer at Eliyan, you will design and develop Ethernet PCS/PMA IPs, optimize digital designs, and collaborate on high-performance products.
Top Skills: Ethernet StandardsIeee 802.3RtlSystemverilog
Reposted 9 Days AgoSaved
In-Office or Remote
7 Locations
Expert/Leader
Expert/Leader
Information Technology • Manufacturing
Lead ASIC and platform development, manage cross-functional teams, oversee project timelines, budgets, and vendor relationships to ensure successful program delivery.
Top Skills: AsicConfluenceJIRAMs Project
Reposted 10 Days AgoSaved
In-Office or Remote
7 Locations
Senior level
Senior level
Information Technology • Manufacturing
The Staff DFT Engineer will define and implement DFT strategies and methodologies, work with cross-functional teams, and support device bring-up for high-volume manufacturing.
Top Skills: 150016871838AtpgDftIeee 1149.XMbistPerlPythonScan InsertShell ScriptingTclVerilog
Reposted 14 Days AgoSaved
In-Office or Remote
9 Locations
6-6 Annually
Senior level
6-6 Annually
Senior level
Information Technology • Manufacturing
As a Staff Digital Verification Engineer, develop verification plans, maintain test environments, and ensure compliance with Ethernet standards while leading junior engineers.
Top Skills: Ci/CdEthernetSystemverilogUvm
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