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As a Signal and Power Integrity Engineer, you'll develop packaging solutions for chiplet interconnects, optimizing performance through simulation, measurement, and collaboration with cross-functional teams.

Lead the frontend digital design of D2D PHY for chiplet systems, optimizing performance and collaborating across teams while mentoring junior designers.

The Principal Digital Verification Engineer will lead technical verification of chiplet products, develop UVM-based test environments, execute verification plans, and mentor junior engineers.

Lead STA signoff processes for complex ASIC designs, defining methodologies and collaborating with design teams to ensure timing closure and optimal performance.

As a Principal Physical Design Engineer, you will lead ASIC development from RTL to GDSII, oversee design flow optimization, and ensure the delivery of high-performance products.

The role involves leading the physical design of ASICs, overseeing all phases from RTL to GDSII, and enhancing design methodologies.